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“I’ve worked with Hardent for many years and have recommended them a few times in the past. Hardent has always been extremely successful with their clients. They have many flexible ways of working with a client and will negotiate a mutually beneficial solution. In our case, they just log into our servers and we are in constant contact via IM, email, phone, etc., but they have all their own design tools as well, so they can work either way. Being in the same time zone makes working with them easy. I am sure you will be happy with the outcome of their work. They’ll hit the ground running much faster than a single contractor would.”
Marshall Johnson,
Sr. Director Global
ASIC/FPGA/IP Development,
ADVA Optical Networking
Sr. Director Global
ASIC/FPGA/IP Development,
ADVA Optical Networking
“Having worked in past with independent electronics design consultants, we appreciate Hardent’s quality, team work and timely service. The company has excellent project management skills, open communication, constant follow-up and a flexible approach. We have been working with Hardent for about two years now. Though initially I was not excited about outsourcing R&D, I feel that I can 100% count on Hardent, as they know their business well and they directed us toward good technical decisions. ”
Michel Bitar,
R&D/ I.T Manager,
Prodco International Inc.
R&D/ I.T Manager,
Prodco International Inc.
FPGA / ASIC Verification Specialist
Apply today to join an electronic design company where you will find the most challenging work, a dynamic team with vast experience and a modern working environment that will enable you to grow, share and thrive.
Job Description:
As an FPGA / ASIC Verification Specialist, you will elaborate verification plans for complex design (device level and system level), develop object-oriented transaction based testbenches, report coverage metrics of SoC ASIC and FPGA blocks, and improve existing HDL based verification flow.
Location:
Hardent’s office in Old Montreal
Required Skills:
- Verilog, SystemVerilog languages
- Open Verification Methodology (OVM) and Universal Verification Methodology (UVM)
- Assertion-based verification and formal verification
- C/C++ language, C-Shell/BASH scripts, makefiles
- Strong analytical skills and attention to detail
- Excellent written and communications ability
- High team spirit
Valuable Knowledge:
- Transaction Level Modeling with SystemC language
- DSP verification using co-simulation with MATLAB / Simulink
- Experience with writing common standards Bus Functional Models
- PLI, Vera or Specman
- Gate Level Verification
- FPGA design methodology
- VHDL hardware description language
Experience and Education:
- Bachelor’s Degree in Electrical Engineering
- At least 4 years of experience as an ASIC or FPGA verification engineer
To apply, send your resume in Word or PDF format to careers@hardent.com.
