Electronic Design: Xilinx & Verification Training Courses

DATE	COURSE	LOCATION	STATUS	SHARE
Oct 15–17, 2019	Advanced Universal Verification Methodology (UVM)	Burlington, MA	Register	Share
Oct 15–17, 2019	Embedded System Design for the Zynq UltraScale+ MPSoC	Live E-Learning	Register	Share
Oct 16–17, 2019	C-based Design - High-Level Synthesis with the Vivado HLx Tool	Coquitlam, BC	Register	Share
Oct 16–17, 2019	Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment	Orlando, FL	Register	Share
Oct 16–18, 2019	Advanced Timing Closure Techniques for the Vivado Design Suite	Montreal, QC	Register	Share
Oct 21–22, 2019	C-based Design - High-Level Synthesis with the Vivado HLx Tool	Ottawa, ON	Register	Share
Oct 21–24, 2019	SystemVerilog for Verification	Orlando, FL	Register	Share
Oct 22–23, 2019	Embedded Design with PetaLinux Tools	Live E-Learning	Register	Share
Oct 22–24, 2019	Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology	Raleigh, NC	Register	Share
Oct 22–24, 2019	Advanced Timing Closure Techniques for the Vivado Design Suite	Orlando, FL	Register	Share

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