| DATE | COURSE | LOCATION | STATUS | SHARE |
| Feb 09–11, 2021 | Embedded System Design for the Zynq UltraScale+ MPSoC | Live E-Learning | Register | |
| Feb 09–11, 2021 | Designing with the Versal ACAP: Architecture and Methodology | Live E-Learning | Register | |
| Feb 10–11, 2021 | Accelerating Applications with the Vitis Unified Software Environment | Live E-Learning |
Register Confirmed
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| Feb 16–17, 2021 | Designing with Versal AI Engine 1 | Live E-Learning | Register | |
| Feb 16–18, 2021 | Advanced UVM | Live E-Learning | Register | |
| Feb 22–23, 2021 | Designing with the Versal ACAP: Programmable Logic Architecture and Methodology | Live E-Learning | Register | |
| Feb 22–24, 2021 | Designing with VHDL | Live E-Learning |
Register Confirmed
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| Feb 23–24, 2021 | C-based Design - High-Level Synthesis with the Vivado HLx Tool | Live E-Learning | Register | |
| Feb 23–24, 2021 | Improve Your Vivado Design Suite Productivity | Live E-Learning | Register | |
| Feb 23–25, 2021 | SystemVerilog for Design | Live E-Learning | Register |
Course Schedule