| DATE | COURSE | LOCATION | STATUS | SHARE |
| Jan 21–23, 2020 | Verilog for Design | Live E-Learning | Register | |
| Jan 21–23, 2020 | Advanced Timing Closure Techniques for the Vivado Design Suite | Huntsville, AL |
Register Confirmed
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| Jan 23–24, 2020 | Essential DSP Implementation Techniques | Live E-Learning | Register | |
| Jan 27–30, 2020 | SystemVerilog for Verification | Live E-Learning | Register | |
| Jan 28–29, 2020 | Designing with the Zynq UltraScale+ RFSoC | Ottawa, ON | Register | |
| Jan 28–29, 2020 | Designing with the Zynq UltraScale+ RFSoC | Orlando, FL | Register | |
| Jan 28–29, 2020 | Embedded Design with PetaLinux Tools | Live E-Learning | Register | |
| Jan 28–29, 2020 | Designing an Integrated PCI Express System | Live E-Learning | Register | |
| Jan 28–30, 2020 | Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology | Burlington, MA | Register | |
| Jan 28–30, 2020 | Advanced Timing Closure Techniques for the Vivado Design Suite | Toronto, ON | Register |
Course Schedule