Electronic Design: Xilinx & Verification Training Courses

DATE	COURSE	LOCATION	STATUS	SHARE
Oct 06–07, 2021	FPGA Design with Vivado Design Suite: The Essentials	Live E-Learning	Register	Share
Oct 06–07, 2021	Designing with Versal AI Engine 1: Architecture and Design Flow	Live E-Learning	Register	Share
Oct 12, 2021	Designing with the Versal ACAP: Network on Chip	Live E-Learning	Register	Share
Oct 12–13, 2021	Designing with the UltraScale and UltraScale+ Architectures	Live E-Learning	Register	Share
Oct 12–14, 2021	Designing with VHDL	Live E-Learning	Register	Share
Oct 12–14, 2021	Advanced UVM	Live E-Learning	Register	Share
Oct 13–14, 2021	Embedded Processor Architecture for the Versal ACAP	Live E-Learning	Register	Share
Oct 18–21, 2021	SystemVerilog for Verification	Live E-Learning	Register	Share
Oct 19–21, 2021	Programmable Logic Architecture for the Versal ACAP	Live E-Learning	Register	Share
Oct 19–21, 2021	Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology	Live E-Learning	Register	Share

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