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Xilinx & Verification Training Courses
Quality training delivered by industry experts
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Course Schedule
Course List
DATE COURSE LOCATION STATUS SHARE
Feb 09–11, 2021 Embedded System Design for the Zynq UltraScale+ MPSoC Live E-Learning Register
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Feb 09–11, 2021 Designing with the Versal ACAP: Architecture and Methodology Live E-Learning Register
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Feb 10–11, 2021 Accelerating Applications with the Vitis Unified Software Environment Live E-Learning Register
Confirmed
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Feb 16–17, 2021 Designing with Versal AI Engine 1 Live E-Learning Register
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Feb 16–18, 2021 Advanced UVM Live E-Learning Register
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Feb 22–23, 2021 Designing with the Versal ACAP: Programmable Logic Architecture and Methodology Live E-Learning Register
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Feb 22–24, 2021 Designing with VHDL Live E-Learning Register
Confirmed
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Feb 23–24, 2021 C-based Design - High-Level Synthesis with the Vivado HLx Tool Live E-Learning Register
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Feb 23–24, 2021 Improve Your Vivado Design Suite Productivity Live E-Learning Register
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Feb 23–25, 2021 SystemVerilog for Design Live E-Learning Register
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Showing results 11 to 20 of 74
Contact HardentContact me
Mary-Ann Conly
Training Coordinator
Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

New Courses

Versal ACAP: Programmable Logic Architecture & Methodology

Versal ACAP: Embedded Processor Architecture & Methodology

Versal ACAP: Network on Chip

Designing with the Versal AI Engine 1 

Designing with the Versal AI Engine 2

Accelerating Applications with Vitis

Vitis AI Platform

Migrating to the Vitis IDE

Advanced Hardware Debugging for Vivado

Advanced Timing Closure for Vivado

See all Courses
Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
Latest News
Contact Us
Hardent Announces Expansion of Xilinx Training in the USA
Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.
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Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies
PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.
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Hardent Becomes Authorized Microchip Design Partner
FPGA design services and support from Hardent will enable Microchip customers to get their products to market more quickly.
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Upcoming Sessions
Jan 26
Designing with the Versal ACAP: Network on Chip
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Jan 26–28
Designing with the Zynq UltraScale+ RFSoC
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Jan 26–28
Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology
Register
Jan 27–28
Designing with Versal AI Engine 2
Register
Complete Course Schedule
Contact Hardent
Mary-Ann Conly
Training Coordinator
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T +1 (514) 284-5252
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We made the decision to work with Hardent as we felt confident that their strategic approach to the development process, combined with their technical expertise and training credentials, would help us to successfully reach our end goal and equip our in-house team with the electronic design knowledge to complete not just this project but other projects in the future.

Stefan Grigoras
Operations Manager
NDT Technologies Inc.
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