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CDNLive Silicon Valley – Santa Clara, USA

Presentation: The Use of Forward Error Correction in the Cadence DisplayPort 1.4 IP Core

Speaker: Tim Corcoran and Avrum Warshawsky

Tuesday, April 11 @ 3:25 p.m.

Santa Clara Convention Center, Santa Clara, CA

Room 208

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Hardent Announces Availability of New Xilinx Versal ACAP Training Courses

New Xilinx Versal ACAP training courses will cover all aspects of designing with the latest Xilinx device category.

Hardent Announces Expansion of Xilinx Training in the USA

Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.

Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies

PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.

Upcoming Sessions

Mar 15–18

Introduction to UVM

Mar 16–18

Embedded System Design for the Zynq UltraScale+ MPSoC

Mar 17–18

Xilinx Partial Reconfiguration Tools and Techniques

Mar 22–23

Designing with the Versal ACAP: Programmable Logic Architecture and Methodology

Complete Course Schedule

Simon Robin

President

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Montreal

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T +1 (514) 284-5252

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