CDNLive Silicon Valley – Santa Clara, USA

Presentation: The Use of Forward Error Correction in the Cadence DisplayPort 1.4 IP Core

Speaker: Tim Corcoran and Avrum Warshawsky

Tuesday, April 11 @ 3:25 p.m.

Santa Clara Convention Center, Santa Clara, CA

Room 208

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Hardent & Xilinx Collaborate to Deliver Complete 8K Ready DisplayPort 1.4 IP Subsystem

New IP solution combining Hardent and Xilinx IP will enable pro A/V designers to take advantage of the full DisplayPort 1.4 feature set to support resolutions up to 8K.

FPGA Design Analysis Using the Vivado Design Suite

Useful commands for FPGA design analysis in the Vivado Design Suite that will help you save time and meet your performance goals!

Hardent & WHDL Named PSS Training Provider For Breker Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Upcoming Sessions

Jul 30–Aug 01

Embedded System Design for the Zynq UltraScale+ MPSoC

Jul 30–Aug 01

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Aug 05–08

SystemVerilog for Verification

Aug 06–08

Embedded System Design for the Zynq UltraScale+ MPSoC

Complete Course Schedule

Simon Robin

President

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HardentMontreal

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Canada

T +1 (514) 284-5252

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