CDNLive Silicon Valley – Santa Clara, USA

Presentation: The Use of Forward Error Correction in the Cadence DisplayPort 1.4 IP Core

Speaker: Tim Corcoran and Avrum Warshawsky

Tuesday, April 11 @ 3:25 p.m.

Santa Clara Convention Center, Santa Clara, CA

Room 208

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Frame Buffer Compression IP Subsystem for TCON IC Manufacturers Launched by Hardent

Proven IP subsystem enables TCON IC manufacturers to leverage new Embedded DisplayPort low power features and significantly reduce frame buffer area using VESA DSC.

Hardent VESA® DSC IP Cores Licensed by Teledyne LeCroy for DisplayPort™ Test Solution

Teledyne LeCroy selects Hardent DSC video compression IP cores for the quantum M42d DisplayPort 2.0 analyzer/generator.

Hardent VESA DSC and FEC IP Cores Licensed by Kinetic Technologies

Kinetic Technologies selects Hardent’s IP cores to create ultra-low power MST hub with VESA DSC support.

Upcoming Sessions

Feb 08–10

Programmable Logic Architecture for the Versal ACAP

Feb 08–09

Advanced Hardware Debugging Techniques Using Vivado Design Suite

Feb 09–10

Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite

Feb 14–15

Designing with Versal AI Engine 1: Architecture and Design Flow

Complete Course Schedule

Simon Robin

President

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HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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