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CDNLive Silicon Valley – Santa Clara, USA

Presentation: The Use of Forward Error Correction in the Cadence DisplayPort 1.4 IP Core

Speaker: Tim Corcoran and Avrum Warshawsky

Tuesday, April 11 @ 3:25 p.m.

Santa Clara Convention Center, Santa Clara, CA

Room 208

Find out more!

Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies

PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.

Hardent Becomes Authorized Microchip Design Partner

FPGA design services and support from Hardent will enable Microchip customers to get their products to market more quickly.

Hardent Joins Forces with Maojet & Fujisoft To Expand Presence in Asia

We recently appointed Maojet Technology Corporation as our new IP representative for Taiwan, and Fujisoft as our new IP representative for Japan. We will be working closely with both companies to develop our IP business within these two key markets.

Upcoming Sessions

Jul 07–09

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Jul 08–09

DSP Design Using System Generator

Jul 14–15

FPGA Design with Vivado Design Suite: The Essentials

Jul 15

Migrating to the Vitis Embedded Software Development IDE Workshop

Complete Course Schedule

Simon Robin

President

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