CDNLive Silicon Valley – Santa Clara, USA

Presentation: The Use of Forward Error Correction in the Cadence DisplayPort 1.4 IP Core

Speaker: Tim Corcoran and Avrum Warshawsky

Tuesday, April 11 @ 3:25 p.m.

Santa Clara Convention Center, Santa Clara, CA

Room 208

Find out more!

Hardent & Xilinx Collaborate to Deliver Complete 8K Ready DisplayPort 1.4 IP Subsystem

New IP solution combining Hardent and Xilinx IP will enable pro A/V designers to take advantage of the full DisplayPort 1.4 feature set to support resolutions up to 8K.

FPGA Design Analysis Using the Vivado Design Suite

Useful commands for FPGA design analysis in the Vivado Design Suite that will help you save time and meet your performance goals!

Hardent & WHDL Named PSS Training Provider For Breker Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Upcoming Sessions

Jan 21–22

Designing with the UltraScale and UltraScale+ Architectures

Jan 21–23

Advanced Timing Closure Techniques for the Vivado Design Suite

Jan 27–30

SystemVerilog for Verification

Jan 28–30

Embedded System Design for the Zynq UltraScale+ MPSoC

Complete Course Schedule

Simon Robin

President

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HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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