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DVCon – San Jose, CA

Our trainer Michael Baird will be presenting a poster on polymorphism in testbench development in UVM.

Stop by February 27 at 10:30 a.m. to hear all about it!

Hardent and Xilinx Collaborate to Deliver Complete 8K Ready DisplayPort 1.4 IP Subsystem

New IP solution combining Hardent and Xilinx IP will enable pro A/V designers to take advantage of the full DisplayPort 1.4 feature set to support resolutions up to 8K.

FPGA Design Analysis Using the Vivado Design Suite

Useful commands for FPGA design analysis in the Vivado Design Suite that will help you save time and meet your performance goals!

Hardent & Willamette HDL Named by Breker Verification Systems As PSS Training Provider For Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Upcoming Sessions

May 28

PCIe Protocol Overview

May 29–30

Designing an Integrated PCI Express System

May 30–31

Designing with the Zynq UltraScale+ RFSoC

Jun 03–06

SystemVerilog for Verification

Complete Course Schedule

Simon Robin

President

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HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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