In this UVM webinar, we will discuss several error injection strategies for UVM verification and illustrate these using a DisplayPort Forward Error Correction (FEC) block as an example.
Not every design block can be 100% tested using predictable input data. Real-world environmental factors such as digital noise must often be considered. For example, in a block designed to recover and repair noise burst errors in a compressed video stream, it is necessary to inject realistic random errors into the stream and verify that these errors are identified and corrected.
You will:
- Discover why controlled error injection is a good approach to verification
- Learn the best place in a UVM testbench to perform error injection
- Hear about the successful, scalable UVM verification approach developed by Hardent and WHDL
- See a real-life example of error injection in the context of a DisplayPort FEC design block used with VESA Display Stream Compression (DSC)
The webinar will be presented by Tim Corcoran, verification specialist and trainer at WHDL, a Hardent training partner.
