An Introduction to the UVM Register Layer
Presenter: Tim Corcoran
This webinar will highlight one key component of the Universal Verification Methodology (UVM), the Register Access Layer (RAL), and demonstrate the power of having an abstract representation of every storage element in the design.
In this webinar, you will:
– Discover the structure of a basic UVM testbench and how the RAL integrates within it
– Learn about the RAL and how it can help when designs and especially memory maps are changing daily
– Learn about the rich RAL APIs available to a test writer to verify individual registers or even whole groups of registers in a block
– Identify the best way to get up to speed on UVM and the RAL
The webinar is presented by Hardent, a leading provider of verification training, and Xilinx Authorized Training Provider. The event is free to attend and includes a live Q&A session.
This webinar is now over, but you can register here to watch a recorded version of the webinar.