DDR Interface

A computer manufacturer migrating to the Virtex-7 platform needed to accelerate their design cycle and required advanced FPGA training for the company’s design team.

As experienced trainers and a Xilinx Authorized Training Provider (ATP), we developed a private class for the customer’s engineers that was delivered by an expert FPGA design engineer. Several aspects of design engineering were presented in the training, including how to implement a high-speed DDR3 memory interface. Issues in signal integrity were also addressed. Our signal integrity experts are able to quickly perform signal integrity analysis and recommend a solution to overcome relevant challenges.

Private training accompanied by signal integrity analysis from Hardent’s electronic design team, equipped the company’s team with the necessary skills to quickly transform their design cycle and bring their product to market on schedule.