Engineering Design Verification

An Application Specific Semiconductor Product (ASSP) manufacturer was on a tight schedule for the development of a new product containing several important new features. The manufacturer was concerned that the rush to get the product to market might compromise its quality.

As the company’s engineering team did not have the right resources to implement the verification environment for this product, they turned to Hardent’s verification experts who designed a comprehensive verification methodology based on SystemVerilog and OVM. Assertions were added on critical interfaces to trap communication problems upfront. To reduce risk and cut development time, the customer’s legacy verification IP was reused by adding OVM wrappers. Constrained-driven random stimulus generation was put in place, which allowed for the detection of special corner-case problems early in the verification cycle while reducing the number of test cases needed. Finally, functional coverage was implemented to ensure the new modules were well verified under all operating conditions.

At the end of the project, the customer possessed a cost-effective, highly configurable, and easy to maintain verification environment that guaranteed a high level of quality assurance. In addition to this, the client’s verification engineers gained expertise in high-level verification methodologies and still have access to support from the Hardent team.