Back to

Timing Closure

Business Challenge

A telecommunications equipment manufacturer was struggling to meet performance expectations on a Virtex-7 device. With more than twenty clock domains, the design was highly complex.

Hardent’s Solution

Drawing on the expertise of our electronic design team, we set up a team to work with the customer to rewrite the timing constraints and map out floorplanning using the Vivado Design Suite software tool.

Impact for the Customer

With Hardent’s assistance, the customer was able to easily meet their timing objectives with every build and was introduced to a new flow that sped up the timing closure process significantly.

Hardent Receives Outstanding Instructor Award for Xilinx Training

Hardent, a leading Xilinx Authorized Training Provider (ATP) and a certified member of the Xilinx Alliance program, has announced that FPGA specialist and trainer Reg Zatrepalek has received an Outstanding Instructor Award for Xilinx training in North America for fiscal year 2017.

New Webinar Schedule: Constraint Management, SystemVerilog, and OpenAMP

Following our recent Introduction to Yocto webinar, Hardent is pleased to announce three more training webinars. These free webinars will address many different aspects of FPGA and embedded system design including constraint management in the Vivado Design Suite, functional coverage in SystemVerilog, and the OpenAMP framework.

Yocto Tutorial: Developing Embedded Linux Systems With Yocto Project

Building and customizing embedded Linux systems can be a challenging task involving several tools. In our recent webinar “An Introduction to Yocto for Embedded Linux Projects Using Xilinx Zynq SoC and MPSoC devices”, we took a look at the Yocto Project and introduced several Yocto concepts before showing how easily specific vendor support could be […]