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Xilinx & Verification Training Courses
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Course List
Course Schedule

Course List

Whether you’re just starting out in your career, or you want to develop specialized skills, our course list has everything you need.

Wondering which course to take? Download our learning path to find the right course level and topic for the next step in your career development.

Vivado Design Suite / FPGA Design
  • Advanced Hardware Debugging Techniques Using Vivado Design Suite
  • Advanced Timing Closure Techniques for the Vivado Design Suite
  • Designing FPGAs Using the Vivado Design Suite 1
  • Designing FPGAs Using the Vivado Design Suite 2
  • Designing FPGAs Using the Vivado Design Suite 3
  • Designing FPGAs Using the Vivado Design Suite 4
  • Designing with the UltraScale and UltraScale+ Architectures
  • FPGA Design with Vivado Design Suite: The Essentials
  • FPGAs for Managers
  • Improve Your Vivado Design Suite Productivity
  • UltraFast Design Methodology
  • Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology
  • Xilinx Partial Reconfiguration Tools and Techniques
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Contact HardentContact me
Mary-Ann Conly
Training Coordinator
Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Upcoming Sessions
Mar 15–18
Introduction to UVM
Register
Mar 16–18
Embedded System Design for the Zynq UltraScale+ MPSoC
Register
Mar 17–18
Xilinx Partial Reconfiguration Tools and Techniques
Register
Mar 22–23
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Complete Course Schedule
Latest News
Contact Us
Hardent Announces Availability of New Xilinx Versal ACAP Training Courses
New Xilinx Versal ACAP training courses will cover all aspects of designing with the latest Xilinx device category.
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Hardent Announces Expansion of Xilinx Training in the USA
Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.
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Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies
PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.
More
Upcoming Sessions
Mar 15–18
Introduction to UVM
Register
Mar 16–18
Embedded System Design for the Zynq UltraScale+ MPSoC
Register
Mar 17–18
Xilinx Partial Reconfiguration Tools and Techniques
Register
Mar 22–23
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Complete Course Schedule
Contact Hardent
Mary-Ann Conly
Training Coordinator
HardentMontreal
450 rue Saint-Pierre, suite 300
Montreal
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QC
H2Y 2M9
Canada
T +1 (514) 284-5252
F +1 (514) 284-5052
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We made the decision to work with Hardent as we felt confident that their strategic approach to the development process, combined with their technical expertise and training credentials, would help us to successfully reach our end goal and equip our in-house team with the electronic design knowledge to complete not just this project but other projects in the future.

Stefan Grigoras
Operations Manager
NDT Technologies Inc.
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