Xilinx & Functional Verification Training

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SystemVerilog for Verification

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Upcoming Sessions

Feb 19–20

C-based Design - High-Level Synthesis with the Vivado HLx Tool

Feb 19–21

SystemVerilog for Design

Feb 21–22

Designing with the UltraScale and UltraScale+ Architectures

Feb 22

SDSoC Development and Methodology (SDSoC license Included)

Complete Course Schedule

Hardent and Xilinx Collaborate to Deliver Complete 8K Ready DisplayPort 1.4 IP Subsystem

New IP solution combining Hardent and Xilinx IP will enable pro A/V designers to take advantage of the full DisplayPort 1.4 feature set to support resolutions up to 8K.

FPGA Design Analysis Using the Vivado Design Suite

Useful commands for FPGA design analysis in the Vivado Design Suite that will help you save time and meet your performance goals!

Hardent & Willamette HDL Named by Breker Verification Systems As PSS Training Provider For Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Upcoming Sessions

Feb 19–20

C-based Design - High-Level Synthesis with the Vivado HLx Tool

Feb 19–21

SystemVerilog for Design

Feb 21–22

Designing with the UltraScale and UltraScale+ Architectures

Feb 22

SDSoC Development and Methodology (SDSoC license Included)

Complete Course Schedule

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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