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SystemVerilog for Verification

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Upcoming Sessions

Nov 26–29

SystemVerilog for Verification

Nov 26–29

SystemVerilog for Verification

Nov 26–27

Designing FPGAs Using the Vivado Design Suite 1

Nov 27–29

Advanced Universal Verification Methodology (UVM)

Complete Course Schedule

New VDC-M (VESA Display Compression-M) IP Cores

VDC-M encoder and decoder IP cores will support the new VESA Display Compression-M standard for mobile devices requiring increased video compression levels of up to 5X.

New On-Demand SystemVerilog for Verification Training Course

Training is a valuable tool for engineering teams wanting to increase productivity, but sometimes there is simply not enough time or money available to travel to a classroom location. Hardent’s new on-demand SystemVerilog for Verification training course bridges this gap and provides students all-around flexibility in learning to use SystemVerilog technology in their verification process.

Hardent IP Portfolio Supports New Features of HDMI 2.1 Specification

VESA DSC and Reed-Solomon FEC IP cores enable HDMI controller manufacturers and IP providers to quickly implement new features of HDMI 2.1 and support higher resolution displays.

Upcoming Sessions

Nov 26–29

SystemVerilog for Verification

Nov 26–29

SystemVerilog for Verification

Nov 26–27

Designing FPGAs Using the Vivado Design Suite 1

Nov 27–29

Advanced Universal Verification Methodology (UVM)

Complete Course Schedule

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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