Learn how to debug your designs quickly and effectively using advanced debug techniques in the Vivado Design Suite.
This Xilinx training will show you how to use the debug tools in the Vivado® Design Suite to address advanced verification/debugging challenges.
As FPGA designs become increasingly more complex, designers continue to look for ways to reduce design and debug time. The powerful, yet easy-to-use, Vivado logic analyzer debug solution helps minimize the amount of time required for verification and debug.
This two-day course will not only introduce you to the cores and tools, and illustrate how to use the triggers effectively, but also show you effective ways to debug designs to enable you to reduce your overall design development time. Students will also learn about the benefits of debug using the in-system IBERT and the required steps for adding it to a design. This training will provide hands-on labs that demonstrate the Vivado debug tool, as well as IBERT and the serial transceiver built-in test features that can help validate the serial link.
As FPGA designs become increasingly more complex, designers continue to look for ways to reduce design and debug time. The powerful, yet easy-to-use, Vivado logic analyzer debug solution helps minimize the amount of time required for verification and debug.
This two-day course will not only introduce you to the cores and tools, and illustrate how to use the triggers effectively, but also show you effective ways to debug designs to enable you to reduce your overall design development time. Students will also learn about the benefits of debug using the in-system IBERT and the required steps for adding it to a design. This training will provide hands-on labs that demonstrate the Vivado debug tool, as well as IBERT and the serial transceiver built-in test features that can help validate the serial link.
Release date
May 29, 2020Level
FPGA 3Training duration
2 daysPrice
USD 1600 or 16 Training CreditsCourse Part Number
HDT-VLA2D-ILTWho Should Attend?
System and logic designers who want to minimize verification and debug timePrerequisites
- Basic knowledge of the VHDL or Verilog language
- Digital design knowledge
- Familiarity with FPGA architecture
Software Tools
- Vivado Design or System Edition 2019.2
Hardware
- Architecture: N/A*
- Demo boards: Zynq UltraScale+ MPSoC ZCU104 board
Skills gained
After completing this comprehensive training, you will have the necessary skills to:- Identify each Vivado IDE debug core and explain its purpose
- Effectively utilize the Vivado logic analyzer
- Implement the Vivado IDE debug cores using both the netlist insertion and HDL instantiation tool flows
- Select effective test points in your design
- Optimize design and core performance when debug cores are used
- Execute various techniques for collecting data including
- File storage
- Script
- Build custom triggers
- Generate an IBERT design
- Use serial I/O analyzer to verify a serial transceiver link
- Use the Vivado debug cores in transceiver designs
Course Outline
- Introduction to Vivado Logic Analyzer
- Debug Cores – Overview
- JTAG to AXI Master Core
- Netlist Insertion Flow
- Lab 1: Inserting a Debug Core Using the Netlist Insertion Flow
- HDL Instantiation Flow
- Lab 2: Adding a Debug Core Using the HDL Instantiation Flow
- Debug Flow in IP Integrator
- Lab 3: Debugging Flow – IPI Block Design
- Introduction to Triggering
- Triggering Using the Trigger State Machine
- Lab 4: Triggering Using the Trigger State Machine
- Capturing Data in Multiple Clock Domains
- Lab 5: Sampling and Capturing Data in Multiple Clock
- Domains
- Trigger on Startup
- Vivado Debug Methodology
- Lab 6: ECO Flow
- Debugging Using TCL Commands
- Lab 7: VIO Tcl Scripting
- Remote Debugging
- Lab 8: Remote Debugging (Optional)
- Transceiver Test and Debug
- Lab 9: IBERT Design
- Lab 10: Serial Transceiver Core Debugging
Lab Descriptions
- Lab 1: Inserting a Debug Core Using the Netlist Insertion Flow - Insert ILA cores into an existing synthesized netlist and debug a common problem.
- Lab 2: Adding a Debug Core Using the HDL Instantiation Flow - Build upon a provided design to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.
- Lab 3: Debugging Flow - IPI Block Design - Add an ILA IP core to a provided block design and connect nets to the core. Observe its behavior using the Vivado logic analyzer.
- Lab 4: Trigger Using the Trigger State Machine
- Lab 5: Sampling and Capturing Data in Multiple Clock Domains
- Lab 6: Vivado Design Suite ECO Flow
- Lab 7: VIO Tcl Scripting - Configure automated analysis.
- Lab 8: Remote Access - Use the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location.
- Lab 9: Using the Integrated Bit Error Rate Tester
- Lab 10: Debugging UltraScale Gigabit Transceivers
Please download the respective PDF of your course: *
* The course version can be found in the training registration form