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Advanced UVM

Get advanced UVM training from verification specialists with this interactive workshop-style class.

This three-day training is designed for UVM users who want to take their skills to the next level and address testbench issues.

Putting together real world testbenches requires more than just knowing the components of the UVM library. Real world testbenches have issues that require knowing how to apply the UVM library to solve these issues. Issues such as multiple interfaces to the DUT, layering stimulus, concurrent process synchronization, dealing with behaviors such as interrupts, reset and multiple response types, and building scalable, reusable testbenches are addressed.

In this Advanced UVM class, you will gain experience in dealing with these and other testbench challenges. The class works through various testbench issues and challenges providing solutions. You will be able to apply these solutions to your testbench. You will also take away from this class detailed real world example testbenches that illustrate solutions to issues providing a great reference in doing your testbench.

Release date

February 9, 2016

Level

UVM 2

Training duration

3 days

Price

USD 2400 or 24 Training Credits

Course Part Number

WHDL-ADVUVM-100

Who Should Attend?

Engineers with UVM experience who want to take their skills to the next level to be able to tackle real world problems.

Prerequisites

  • This is an advanced class and students are expected to have actual UVM experience or have taken an UVM Introductory course plus some experience

Software Tools

  • Questa Simulator 10.4c

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Create scalable, reusable UVM testbench structures
  • Deal with thorny issues such as reset, interrupts and synchronization across multiple components
  • Apply advanced stimulus related techniques such as layered stimulus or complex scenarios
  • Apply advanced analysis techniques such as scoreboard draining
  • Apply advanced register integration and techniques to your register model

Course Outline

  • In this Advanced UVM class, a large portion of time is spent in interactive discussion, “whiteboarding,” and applying the topics to the student’s application.
  • The agendas for Day 1 and Day 2 will present a series of ordered topics, while the agenda for Day 3 will vary based on relevance and interest. A few topics from the available list will be selected during the class, based on the student’s training goals.
  • Day 1
    • DUT-TB Interface and Configuration
      • Encapsulation
      • DUT-TB Communication
      • DUT-TB Parameter sharing
      • DUT-TB Configuration and Distribution: Configuration object creation, Configuration object distribution
    • Container Classes
      • Queues
      • Pools
    • Template Method Pattern and UVM Callbacks
      • Template Method Pattern
      • UVM Callbacks
      • LAB – Callbacks
    • Synchronization Classes
      • Events
      • Barriers
      • LAB – Synchronization
  • Day 2
    • Phasing
      • Phase callbacks: Draining using callbacks, Phase awareness using Callbacks
      • Phase awareness using multiple domains
    • Message Catching (Demoting)
      • LAB – Heartbeat and more
    • Factory – Beyond the basics
    • Configurability using Polymorphism
      • Configurabilty
      • Polymorphism
      • Example Polymorphic testbench
    • Virtual Interface Issues
      • Virtual Interface wrappers
      • Interface proxy classes
    • Virtual Sequences
      • Virtual Sequences
      • API sequence “calls”
      • Coordination of multiple interfaces
  • Day 3
    • Response handling
      • Non-virtual sequence responses
      • Virtual sequence responses
    • Interrupt handling
      • Interrupt monitoring
      • Interrupt Service Routines (ISR)
    • Reset
    • Dynamic error injection
    • Reuse
      • Interface (agent) reuse
      • Block (environment) reuse
      • Block-to-top reuse
    • Advanced UVM Registers
      • UVM register model integration: Direct environment integration, Register layer integration
      • UVM register Memory Allocation Manager
      • Extension object
      • Register model and scoreboards
      • Custom (quirky) registers
      • Backdoor access
    • Performance Improvements
      • Prototype pattern
      • Memory manager
    • Interface classes
    • Command line processing

Special Comments

Please download the respective PDF of your course: *

  • Advanced_Universal_Verification_Methodology_UVM_whdl-advuvm-100-2.1_ilt.pdf

Enquire Now

Related Courses

Introduction to UVM

View course

Introduction to UVM (On-Demand)

View course
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