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Xilinx & Verification Training Courses
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Advanced VHDL for Verification

Advanced VHDL for verification training designed to help you take your VHDL verification skills to the next level.

A 3-day course emphasizing behavioral techniques, testbench strategies, and design management. The 3-day Advanced VHDL class is aimed at experienced VHDL users who wish to take their use of the language to a higher level. The course is a mix of lecture and lab-exercises.

Release date

June 27, 2016

Level

2

Training duration

3 days

Price

USD 2400 or 24 Training Credits

Course Part Number

HDT-ADVVHDL-100

Who Should Attend?

Experienced VHDL writers who wish to take their use of the language to a higher level in the areas of behavioral modeling and verification.

Prerequisites

  • Introduction to VHDL course or equivalent experience

Software Tools

  • Questa Simulator 10.4c

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Create an OVM testbench structure using the OVM library base classes and the OVM factory
  • Use behavioral modeling techniques to develop VHDL-based scoreboards and predictor models
  • Use new capabilities included in recent updates of VHDL for verification
  • Apply advanced stimulus-related techniques such as random stimulus generation and LFSRs
  • Apply advanced analysis and scoreboarding techniques such as MISR signatures and monitors
  • Increase automation and productivity by using makefiles and version control systems

Course Outline

  • Advanced VHDL language topics
  • Access type
  • Dynamic memory allocation
  • Resolution Functions
  • Shared variables
  • Guarded blocks
  • File I/O
  • Behavioral modeling
  • Thinking Behaviorally
  • Basic algorithms
  • Data Structures
  • System modeling
  • Handshaking/protocol techniques
  • Functional Verification
  • Stimulus generation techniques
  • Random stimulus generation
  • LFSR models
  • External files
  • Sweepers
  • Verification using signatures
  • High-level debugging using Monitors
  • Design Management
  • Using Makefiles
  • Automating compilation/verification
  • Source Code Control
  • Intro to RCS

Please download the respective PDF of your course: *

  • Advanced_VHDL_for_Verification_hdt-advvhdl-100_ilt.pdf

Enquire Now

* The course version can be found in the training registration form

Related Course

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Mary-Ann Conly
Training Coordinator

Course Schedule

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