Home
  • About Us
    • History
    • Mission
    • Team
    • Partners & Memberships
    • Customer Stories
  • Applications
    • Video
    • Automotive
    • Aerospace & Defense
    • Industrial
    • Telecommunications
  • News
    • Press Releases
    • Blog
    • Events
  • Careers
  • Contact
  • LinkedIn
  • Twitter
Xilinx & Verification Training Courses
Quality training delivered by industry experts
Back to
Course scheduleCourse list

Designing FPGAs Using the Vivado Design Suite 4

With this course you will get advanced Xilinx Vivado training that will enable you to improve FPGA performance and utilization, as well as increase your productivity.

Learn how to use the advanced aspects of the Vivado® Design Suite and Xilinx hardware.

The focus is on:
  • Applying timing constraints for source-synchronous and system-synchronous interfaces
  • Utilizing floorplanning techniques
  • Employing advanced implementation options
  • Utilizing Xilinx security features
  • Identifying advanced FPGA configurations
  • Debugging a design at the device startup phase
  • Using Tcl scripting in non-project batch flows


This is the final course in the Designing FPGAs Using the Vivado Design Suite series.

Release date

13 April, 2017

Level

FPGA 4

Training duration

2 day

Price

USD 1600 or 16 Training Credits

Course Part Number

FPGA-VDES4-ILT

Who Should Attend?

Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity

Prerequisites

  • Designing FPGAs Using the Vivado Design Suite 2 course
  • Designing FPGAs Using the Vivado Design Suite 3 course
  • At least six months of design experience with Xilinx tools and FPGAs

Software Tools

  • Vivado Design or System Edition 2020.1

Hardware

  • Architecture: UltraScale™ family
  • Demo board: Zynq® UltraScale+™ ZCU104 board

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
  • Analyze a timing report to identify how to center the clock in the data eye
  • Utilize floorplanning techniques to improve design performance
  • Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
  • Utilize Xilinx security features, bitstream encryption, and authentication using AES for design and IP security
  • Identify advanced FPGA configurations, such as daisy chains and gangs, for configuring multiple FPGAs in a design
  • Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset
  • Use Tcl scripting in non-project batch flows to synthesize, implement, and generate custom timing reports

Course Outline

  • UltraFast Design Methodology: Design Closure – Introduces the UltraFast design methodology guidelines covered in this course. {Lecture}
  • Scripting in Vivado Design Suite Non-Project Mode – Write Tcl commands in the non-project batch flow for a design. {Lecture, Lab}
  • Hierarchical Design – Overview of the hierarchical design flows in the Vivado Design Suite.{Lecture}
  • Managing Remote IP – Store IP and related files remote to the current working project directory.{Lecture, Lab}
  • I/O Timing Scenarios – Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data. {Lecture}
  • System-Synchronous I/O Timing – Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface. {Lecture, Demo}
  • Source-Synchronous I/O Timing – Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface.{Lecture, Lab}
  • Timing Constraints Priority – Identify the priority of timing constraints. {Lecture}
  • Case Analysis – Understand how to analyze timing when using multiplexed clocks in a design. {Lecture}
  • Introduction to Floorplanning – Introduction to floorplanning and how to use Pblocks while floorplanning. {Lecture}
  • Design Analysis and Floorplanning – Explore the pre- and post-implementation design analysis features of the Vivado IDE. {Lecture, Lab}
  • Congestion - Identifies congestion and addresses congestion issues. {Lecture}
  • Introduction to the Xilinx XHub Stores – Introduces the Xilinx XHub Stores. {Lecture, Demo}
  • Incremental Compile Flow – Utilize the incremental compile flow when making last-minute RTL changes. {Lecture, Lab}
  • Timing Closure Using Physical Optimization Techniques – Use physical optimization techniques for timing closure. {Lecture}
  • Vivado Design Suite ECO Flow – Use the ECO flow to make changes to a previously implemented design and apply changes to the original design. {Lecture, Lab}
  • Power Management Techniques – Identify techniques used for low power design. {Lecture}
  • Daisy Chains and Gangs in Configuration – Introduces advanced configuration schemes for multiple FPGAs. {Lecture}
  • Bitstream Security – Understand the Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication. {Lecture, Demo}
  • Vivado Design Suite Debug Methodology – Understand and follow the debug core recommendations. Employ the debug methodology for debugging a design using the Vivado logic analyzer. {Lecture}
  • Trigger and Debug at Device Startup – Debug the events around the device startup. {Lecture, Demo}
  • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer – Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer. {Lecture, Lab}
  • Debugging the Design Using Tcl Commands – Use Tcl scripting for VLA designs for adding probes and making connections to probes. {Lecture, Lab}
  • Using Procedures in Tcl Scripting - Employ procedures in Tcl scripting. {Lecture}
  • Using Lists in Tcl Scripting – Employ lists in Tcl scripting.{Lecture}
  • Using Regular Expressions in Tcl Scripting – Use regular expressions to find a pattern in a text file while scripting an action in the Vivado Design Suite.{Lecture, Lab}
  • Debugging and Error Handling in Tcl Scripts – Understand how to debug errors in a Tcl script. {Lecture}

Please download the respective PDF of your course: *

  • Designing_FPGAs_Using_the_Vivado_Design_Suite_4_fpga-vdes4_2020-1_ilt_H.pdf

Enquire Now

* The course version can be found in the training registration form

Related Courses

Advanced Timing Closure Techniques for the Vivado Design Suite

View course

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

View course
Contact HardentContact me
Your Trainer, Reg
Have a question about the course?

Course Schedule

  • Enquire Now
Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
Upcoming Sessions
Jan 27–28
Designing with Versal AI Engine 2
Register
Feb 01–04
Introduction to UVM
Register
Feb 02–03
Designing with the Versal ACAP: Embedded Processor Architecture and Methodology
Register
Feb 03–04
Advanced Hardware Debugging Techniques Using Vivado Design Suite
Register
Complete Course Schedule
Latest News
Contact Us
Hardent Announces Availability of New Xilinx Versal ACAP Training Courses
New Xilinx Versal ACAP training courses will cover all aspects of designing with the latest Xilinx device category.
More
Hardent Announces Expansion of Xilinx Training in the USA
Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.
More
Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies
PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.
More
Upcoming Sessions
Jan 27–28
Designing with Versal AI Engine 2
Register
Feb 01–04
Introduction to UVM
Register
Feb 02–03
Designing with the Versal ACAP: Embedded Processor Architecture and Methodology
Register
Feb 03–04
Advanced Hardware Debugging Techniques Using Vivado Design Suite
Register
Complete Course Schedule
Contact Hardent
Your Trainer, Reg
Have a question about the course?
HardentMontreal
450 rue Saint-Pierre, suite 300
Montreal
,
QC
H2Y 2M9
Canada
T +1 (514) 284-5252
F +1 (514) 284-5052
Tick to hear more from Hardent by email. This includes our newsletter, details about offers, new courses, and events. You can opt out at any time. For further information, please refer to our privacy policy.

Time to market was one of our first considerations in choosing Hardent to design a PCI communication bridge. They grasped the project requirements in a matter of days. Their impressive expertise and responsiveness made the development process very smooth, as if they were working right down the hall.

Nicolas Gonthier
Hardware Design Manager
Verint Systems Canada Inc.
More testimonials
Training Partners
WHDL logo
Hardent © 2002-2021.
All rights reserved.
  • Privacy Policy
We use cookies to ensure that we give you the best experience on our website. By continuing to use this website, you consent to our use of cookies. OK