ASIC Emulation Challenge
ASIC design presents many challenges to the design team. There is often a requirement to employ FPGAs to emulate the functionality of ASIC devices before committing to the final tapeout and ASIC prototype. However, FPGAs can also bring unique challenges of their own during the design process. This may be exasperated by a desire to keep the HDL code as close as possible to the final ASIC implementation. Issues such as multiple clocks, iterative and incremental design flows, and diverse team based designs further complicate the process.In order to address the needs of engineers and system architects who are using or plan to use Vivado and 7-Series 2000T devices for ASIC emulation, a quick start course has been created. The objective of this course is to increase the number of iterations per day by preserving the implementation of modules that are unaltered from one implementation to the next. Often it is sufficient for FPGA emulation platforms to run at lower clock speeds than the final ASIC, so tradeoffs between FPGA clock rate and Vivado run time will also be explored. The course is 2 days duration and is a compressed format containing only lecture material with no hands-on labs.
Release dateApril 4, 2013
Training duration2 days
PriceUSD 1600 or 16 Training Credits
Course Part NumberHDT-VIVA40000-ILT
Who Should Attend?Digital designers and system architects who need to learn the Vivado Design Suite for use in ASIC emulation.
- Intermediate knowledge of the VHDL or Verilog language
- Digital design knowledge
- FPGA design experience
- Essential Tcl Scripting for the Vivado Design Suite
- Xilinix ISE design suite: Login or System Edition 14.1
- MathWorks MATLAB 2014b
- Architecture: 7 Series FPGAs**
- Demo board: Kintex™-7 FPGA KC705 board**
Skills gainedAfter completing this comprehensive training, you will have the necessary skills to:
- Identify the Vivado IDE design flows
- Identify the source file sets (HDL, XDC, simulation)
- Implement an HDL design using the Vivado tool suite
- Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.). Describe how min/max timing analysis information is conveyed in a timing report and used to analyze setup and hold checks
- Utilize the custom timing report options to build optimal timing reports
- Make appropriate I/O timing constraints and design modifications for any interface
- Utilize the most advanced features (area constraints) of the Vivado IDE to improve design performance and utilization
- Use scripting in project-based and non-project batch flows to synthesize, implement, and generate custom timing reports
- Essential Vivado – Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints, and basic timing reports. Discusses key features and benefits, how to manage designs, and implement by using the Vivado software tool.
- Vivado XDC – Learn how to use Xilinx Design Constraints (XDC – based on the industry-standard Synopsys Design Constraints) to constrain a design. Includes essential Vivado Tcl commands. Explores the underlying design database and how the Vivado Design Suite applies constraints to the FPGA implementation. Discusses Static Timing Analysis mechanisms and how to read and interpret advanced timing reports. Examines clocks, clock constraint propagation, advanced timing exceptions, path specific timing constraints, and advanced IO constraints.
- Advanced Vivado – Learn to increase design utilization and achieve repeatable results using the Vivado software tool. Discusses the scripting environment of the Vivado Design Suite and how to use the project-based and non-project batch flows. Explores the most sophisticated aspects of the Vivado Design Suite and Xilinx hardware. Utilize floor planning techniques to maintain consistent successful results. Discusses incremental design flow, design iterations, hierarchical design flow, design preservation flow, design partitions, and team based design considerations.
Please download the respective PDF of your course: *
* The course version can be found in the training registration form