This comprehensive course is a thorough introduction to SystemVerilog constructs for design. This class addresses writing RTL code using the new constructs available in SystemVerilog. New data types, structs, unions, arrays, procedural blocks, and re-usable tasks, functions, and packages, are all covered. The information gained can be applied to any digital design. This course combines insightful lectures with practical lab exercises to reinforce key concepts. In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop RTL designs.
Release dateJuly 2016
Training duration2 Days
PriceUSD 1600 or 16 Training Credits
Course Part NumberLANG-SVDES
Who Should Attend?FPGA designers and logic designers
- Verilog design experience or completion of Designing with Verilog
- Vivado Design or System Edition 2016.1
- Questa Sim Prime Simulator 10.5b
- Architecture: N/A
- Demo board: Kintex-7 FPGA KC705 board
Skills gainedAfter completing this comprehensive training, you will have the necessary skills to:
- Describe the features and benefits of using SystemVerilog for RTL design
- Identify the new data types supported in SystemVerilog
- Use an enumerated data type for coding a finite state machine (FSM)
- Explain how to use structures, unions, and arrays
- Describe the new procedural blocks and analyze the affected synthesis results
- Define the enhancements and ability to reuse tasks, functions, and packages
- Identify how to simplify module definitions and instantiations using interfaces
- Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
- Target and optimize Xilinx FPGAs by using SystemVerilog
- Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
- Download a complete SystemVerilog design to an evaluation board
- Introduction to SystemVerilog
- Data Types
- Demo: SystemVerilog Integer Data Types
- Lab 1: SystemVerilog Data Types
- Structures, Unions, and Arrays
- Lab 2: Structures and Unions
- Additional Operators in System Verilog
- Procedural Statements and Flow Control
- Lab 3: always_ff and always_comb Procedural Blocks
- Functions, Tasks, and Packages
- Lab 4: Packages
- Lab 5: Interfaces and Design Download
- Targeting Xilinx FPGAs
- Lab 1: SystemVerilog Data Types - Use enumerated data types to build a finite state machine and perform synthesis to analyze the results.
- Lab 2: Structures and Unions - Learn about packed and unpacked structures and unions and how to access their members.
- Lab 3: always_ff and always_comb Procedural Blocks - Learn to use the new procedural blocks always_comb, always_ff, and always_latch to produce the intended synthesized results.
- Lab 4: Packages - Create a new package and import that package into the module.
- Lab 5: Interfaces and Design Download - Use an interface to simplify the module inputs and outputs. Download and verify the design in-circuit.
Please download the respective PDF of your course: *
* The course version can be found in the training registration form