Home
  • About Us
    • History
    • Mission
    • Team
    • Partners & Memberships
    • Customer Stories
  • Applications
    • Video
    • Automotive
    • Aerospace & Defense
    • Industrial
    • Telecommunications
  • News
    • Press Releases
    • Blog
    • Events
  • Careers
  • Contact
  • LinkedIn
  • Twitter
Xilinx & Verification Training Courses
Quality training delivered by industry experts
Back to
Course scheduleCourse list

Designing with the Versal ACAP: Embedded Processor Architecture and Methodology

2-day course focused on the Versal ACAP embedded processor architecture.

This course helps you to learn about Versal™ ACAP embedded processor architecture and design methodology.

The emphasis of this course is on:
  • Reviewing the architecture of the Versal ACAP
  • Describing the different engines available in the Versal architecture and what resources they contain
  • Utilizing the hardened blocks available in the Versal architecture
  • Using the design tools and methodology provided by Xilinx to create complex systems
  • Describing the network on chip (NoC) and AI Engine concepts and their architectures
  • Performing system-level simulation and debugging

Release date

December 2020

Level

ACAP 1

Training duration

2 days

Price

USD 1800 or 18 Training Credits

Course Part Number

HDT-ACAP-ARCH-SW

Who Should Attend?

Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Xilinx Versal ACAP device

Prerequisites

  • Comfort with the C/C++ programming language
  • Vitis™ IDE software development flow
  • Zynq® UltraScale+ MPSoCs

Software Tools

  • Vivado Design Suite 2020.2
  • Vitis unified software platform 2020.2
  • PetaLinux Tools 2020.2

Hardware

  • Architecture: Xilinx Versal ACAPs

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Describe the Versal ACAP architecture at a high level
  • Describe the various engines in the Versal ACAP device
  • Use the various blocks from the Versal architecture to create complex systems
  • Perform system-level simulation and debugging
  • Identify and apply different design methodologies

Course Outline

  • Introduction - Talks about the need for Versal devices and gives an overview of the different Versal families. {Lecture}
  • Architecture Overview - Provides a high-level overview of the Versal architecture, illustrating the various engines available in the Versal architecture. {Lecture}
  • Design Tool Flow - Maps the various engines in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab}
  • Processing System - Reviews the Cortex™-A72 processor APU and Cortex-R5 processor RPU that form the Scalar Engine. The platform management controller (PMC), processing system manager (PSM), I/O peripherals, and PS-PL interfaces are also covered. {Lecture}
  • PMC and Boot and Configuration - Describes the platform management controller, platform loader and manager (PLM) software and boot and configuration. {Lecture, Lab}
  • System Interrupts - Discusses the different system interrupts and interrupt controllers. {Lecture}
  • Timers, Counters, and RTC - Provides an overview of timers and counters, including the system counter, triple timer counter (TTC), watchdog timer, and real-time clock (RTC). {Lecture}
  • Software Build Flow - Provides an overview of the different build flows, such as the do it yourself, Yocto Project, and PetaLinux tool flows. {Lecture, Lab}
  • Software Stack - Reviews the Versal ACAP bare-metal, FreeRTOS, and Linux software stack and their components. {Lecture}
  • AI Engine - Discusses the AI Engine array architecture, terminology, and AIE interfaces. {Lecture}
  • Device Memory - Describes the available memory resources, such as block RAM, UltraRAM, LUTRAM, embedded memory, OCM, and DDR. The integrated memory controllers are also covered. {Lecture}
  • Programming Interfaces - Reviews the various programming interfaces in the Versal ACAP. {Lecture}
  • Application Partitioning - Covers what application partitioning is and how the mapping of resources based on the models of computation can be performed. {Lecture}
  • PCI Express and CCIX - Provides an overview of the CCIX PCIe module and describes the PL and CPM PCIe blocks. {Lecture}
  • Power Solutions - Discusses the power domains in the Versal ACAP as well as power optimization and analysis techniques.{Lecture}
  • Security Features - Describes the security features of the Versal ACAP. {Lecture}
  • System Simulation - Explains how to perform system-level simulation in a Versal ACAP design. {Lecture}
  • System Design Methodology - Reviews the Xilinx-recommended methodology for designing a system. {Lecture}

Please download the respective PDF of your course: *

  • Designing_with_the_Versal_ACAP_Embedded_Processor_Architecture_and_Methodology_hdt-acap-arch-sw_2020-2_ilt_H.pdf

* The course version can be found in the training registration form

Related Courses

Designing with the Versal ACAP: Programmable Logic Architecture and Methodology

View course

Designing with the Versal ACAP: Network on Chip

View course

Designing with Versal AI Engine 1

View course
Contact HardentContact me
Your Trainer, Reg
Have a question about the course?

Course Schedule

  • Feb 02–03, 2021
    Live E-Learning
    Register
  • Mar 01–02, 2021
    Live E-Learning
    Register
  • Mar 29–30, 2021
    Live E-Learning
    Register
Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
Upcoming Sessions
Jan 19–20
Embedded Design with PetaLinux Tools
Register
Jan 20–21
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Jan 21
Migrating to the Vitis Embedded Software Development IDE Workshop
Register
Jan 26
Designing with the Versal ACAP: Network on Chip
Register
Complete Course Schedule
Latest News
Contact Us
Hardent Announces Expansion of Xilinx Training in the USA
Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.
More
Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies
PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.
More
Hardent Becomes Authorized Microchip Design Partner
FPGA design services and support from Hardent will enable Microchip customers to get their products to market more quickly.
More
Upcoming Sessions
Jan 19–20
Embedded Design with PetaLinux Tools
Register
Jan 20–21
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Jan 21
Migrating to the Vitis Embedded Software Development IDE Workshop
Register
Jan 26
Designing with the Versal ACAP: Network on Chip
Register
Complete Course Schedule
Contact Hardent
Your Trainer, Reg
Have a question about the course?
HardentMontreal
450 rue Saint-Pierre, suite 300
Montreal
,
QC
H2Y 2M9
Canada
T +1 (514) 284-5252
F +1 (514) 284-5052
Tick to hear more from Hardent by email. This includes our newsletter, details about offers, new courses, and events. You can opt out at any time. For further information, please refer to our privacy policy.

I’ve worked with Hardent for many years and have recommended them a few times in the past. Hardent has always been extremely successful with their clients. They have many flexible ways of working with a client and will negotiate a mutually beneficial solution.

In our case, they just log into our servers and we are in constant contact via IM, email, phone, etc., but they have all their own design tools as well, so they can work either way. Being in the same time zone makes working with them easy. I am sure you will be happy with the outcome of their work. They’ll hit the ground running much faster than a single contractor would.

Marshall Johnson
Sr. Director Global ASIC/FPGA/IP Development
ADVA Optical Networking
More testimonials
Training Partners
WHDL logo
Hardent © 2002-2021.
All rights reserved.
  • Privacy Policy
We use cookies to ensure that we give you the best experience on our website. By continuing to use this website, you consent to our use of cookies. OK