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Xilinx & Verification Training Courses
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Designing with the Versal ACAP: Embedded Processor Architecture and Methodology

2-day course focused on the Versal ACAP embedded processor architecture.

This course helps you to learn about Versal™ ACAP embedded processor architecture and design methodology.

The emphasis of this course is on:
  • Reviewing the architecture of the Versal ACAP
  • Describing the different engines available in the Versal architecture and what resources they contain
  • Utilizing the hardened blocks available in the Versal architecture
  • Using the design tools and methodology provided by Xilinx to create complex systems
  • Describing the network on chip (NoC) and AI Engine concepts and their architectures
  • Performing system-level simulation and debugging

Release date

December 2020

Level

ACAP 1

Training duration

2 days

Price

USD 1800 or 18 Training Credits

Course Part Number

HDT-ACAP-ARCH-SW

Who Should Attend?

Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Xilinx Versal ACAP device

Prerequisites

  • Comfort with the C/C++ programming language
  • Vitis™ IDE software development flow
  • Zynq® UltraScale+ MPSoCs

Software Tools

  • Vivado Design Suite 2020.2
  • Vitis unified software platform 2020.2
  • PetaLinux Tools 2020.2

Hardware

  • Architecture: Xilinx Versal ACAPs

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Describe the Versal ACAP architecture at a high level
  • Describe the various engines in the Versal ACAP device
  • Use the various blocks from the Versal architecture to create complex systems
  • Perform system-level simulation and debugging
  • Identify and apply different design methodologies

Course Outline

  • Introduction - Talks about the need for Versal devices and gives an overview of the different Versal families. {Lecture}
  • Architecture Overview - Provides a high-level overview of the Versal architecture, illustrating the various engines available in the Versal architecture. {Lecture}
  • Design Tool Flow - Maps the various engines in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab}
  • Processing System - Reviews the Cortex™-A72 processor APU and Cortex-R5 processor RPU that form the Scalar Engine. The platform management controller (PMC), processing system manager (PSM), I/O peripherals, and PS-PL interfaces are also covered. {Lecture}
  • PMC and Boot and Configuration - Describes the platform management controller, platform loader and manager (PLM) software and boot and configuration. {Lecture, Lab}
  • System Interrupts - Discusses the different system interrupts and interrupt controllers. {Lecture}
  • Timers, Counters, and RTC - Provides an overview of timers and counters, including the system counter, triple timer counter (TTC), watchdog timer, and real-time clock (RTC). {Lecture}
  • Software Build Flow - Provides an overview of the different build flows, such as the do it yourself, Yocto Project, and PetaLinux tool flows. {Lecture, Lab}
  • Software Stack - Reviews the Versal ACAP bare-metal, FreeRTOS, and Linux software stack and their components. {Lecture}
  • AI Engine - Discusses the AI Engine array architecture, terminology, and AIE interfaces. {Lecture}
  • Device Memory - Describes the available memory resources, such as block RAM, UltraRAM, LUTRAM, embedded memory, OCM, and DDR. The integrated memory controllers are also covered. {Lecture}
  • Programming Interfaces - Reviews the various programming interfaces in the Versal ACAP. {Lecture}
  • Application Partitioning - Covers what application partitioning is and how the mapping of resources based on the models of computation can be performed. {Lecture}
  • PCI Express and CCIX - Provides an overview of the CCIX PCIe module and describes the PL and CPM PCIe blocks. {Lecture}
  • Power Solutions - Discusses the power domains in the Versal ACAP as well as power optimization and analysis techniques.{Lecture}
  • Security Features - Describes the security features of the Versal ACAP. {Lecture}
  • System Simulation - Explains how to perform system-level simulation in a Versal ACAP design. {Lecture}
  • System Design Methodology - Reviews the Xilinx-recommended methodology for designing a system. {Lecture}

Please download the respective PDF of your course: *

  • Designing_with_the_Versal_ACAP_Embedded_Processor_Architecture_and_Methodology_hdt-acap-arch-sw_2020-2_ilt_H.pdf

Related Courses

Designing with the Versal ACAP: Programmable Logic Architecture and Methodology

View course

Designing with the Versal ACAP: Network on Chip

View course

Designing with Versal AI Engine 1: Architecture and Design Flow

View course
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Course Schedule

  • May 05–06, 2021
    Live E-Learning
    Register
    Confirmed
  • Jun 14–15, 2021
    Live E-Learning
    Register
Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
Upcoming Sessions
Apr 20–22
Embedded System Design for the Zynq UltraScale+ MPSoC
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Apr 26–29
Introduction to UVM
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Apr 26–27
Embedded Design with PetaLinux Tools
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Apr 27–28
Designing with Xilinx Serial Transceivers
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Complete Course Schedule
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Upcoming Sessions
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Embedded System Design for the Zynq UltraScale+ MPSoC
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Apr 26–29
Introduction to UVM
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Apr 26–27
Embedded Design with PetaLinux Tools
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Apr 27–28
Designing with Xilinx Serial Transceivers
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Complete Course Schedule
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Have a question about the course?
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Stefan Grigoras
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NDT Technologies Inc.
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