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Xilinx & Verification Training Courses
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Designing with the Versal ACAP: Network on Chip

1-day training specifically focused on the Versal ACAP network on chip (NoC).

This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.

The emphasis of this course is on:
  • Enumerating the major components comprising the NoC architecture in the Versal ACAP
  • Implementing a basic design using the NoC
  • Configuring the NoC for efficient data movement

Release date

December 2020

Level

ACAP 2

Training duration

1 day

Price

USD 900 or 9 Training Credits

Course Part Number

ACAP NOC

Who Should Attend?

Hardware developers and system architects whether migrating from existing Xilinx devices or starting out with the Versal ACAP devices

Prerequisites

  • Any Xilinx device architecture class
  • Familiarity with the Vivado® Design Suite

Software Tools

  • Vivado Design Suite 2020.2

Hardware

  • Architecture: Xilinx Versal ACAPs

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Identify the major network on chip components in the Versal ACAP
  • Include the necessary components to access the NoC from the PL
  • Configure connection QoS for efficient data movement

Course Outline

  • Architecture Overview for Existing Xilinx Users - Introduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices. {Lecture}
  • Versal ACAPs Compared to Zynq UltraScale+ Devices - The Versal ACAP has a number of similarities to the Zynq® UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context. {Lecture}
  • NoC Introduction and Concepts - Reviews the basic vocabulary and high-level operations of the NoC. {Lecture, Lab}
  • NoC Architecture - Provides the first deep dive into the sub-blocks of the NoC and how they are used. Describes how the NoC is accessed from the programmable logic. {Lecture}
  • Design Tool Flow Overview - Designers come to the Versal ACAP devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the Xilinx toolbox. {Lecture}
  • NoC DDR Memory Controller - The integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC's DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use. {Lecture}
  • NoC Performance Tuning - Synthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance. {Lecture, Lab}
  • System Design Migration - Describes how different users will leverage tools and processes to migrate their designs to the Versal ACAP devices. {Lecture}

Please download the respective PDF of your course: *

  • Designing_with_the_Versal_ACAP_Network_on_Chip_acap-noc_2020-2_ilt_H.pdf

* The course version can be found in the training registration form

Related Courses

Designing with the Versal ACAP: Programmable Logic Architecture and Methodology

View course

Designing with the Versal ACAP: Embedded Processor Architecture and Methodology

View course

Designing with Versal AI Engine 1

View course
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Your Trainer, Rick
Have a question about the course?

Course Schedule

  • Jan 26, 2021
    Live E-Learning
    Register
  • Feb 24, 2021
    Live E-Learning
    Register
  • Mar 31, 2021
    Live E-Learning
    Register
Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
Upcoming Sessions
Jan 19–20
Embedded Design with PetaLinux Tools
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Jan 20–21
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Jan 21
Migrating to the Vitis Embedded Software Development IDE Workshop
Register
Jan 26
Designing with the Versal ACAP: Network on Chip
Register
Complete Course Schedule
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Upcoming Sessions
Jan 19–20
Embedded Design with PetaLinux Tools
Register
Jan 20–21
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Jan 21
Migrating to the Vitis Embedded Software Development IDE Workshop
Register
Jan 26
Designing with the Versal ACAP: Network on Chip
Register
Complete Course Schedule
Contact Hardent
Your Trainer, Rick
Have a question about the course?
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I’ve worked with Hardent for many years and have recommended them a few times in the past. Hardent has always been extremely successful with their clients. They have many flexible ways of working with a client and will negotiate a mutually beneficial solution.

In our case, they just log into our servers and we are in constant contact via IM, email, phone, etc., but they have all their own design tools as well, so they can work either way. Being in the same time zone makes working with them easy. I am sure you will be happy with the outcome of their work. They’ll hit the ground running much faster than a single contractor would.

Marshall Johnson
Sr. Director Global ASIC/FPGA/IP Development
ADVA Optical Networking
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