Designing with VHDL

This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs

After completing this comprehensive training, you will have the necessary skills to:

• Implement the VHDL portion of coding for synthesis
• Identify the differences between behavioral and structural coding styles
• Distinguish coding for synthesis versus coding for simulation
• Use scalar and composite data types to represent information
• Use concurrent and sequential control structure to regulate information flow
• Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)
• Simulate a basic VHDL design
• Write a VHDL testbench and identify simulation-only constructs
• Identify and implement coding best practices
• Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
• Create and manage designs within the Vivado Design Suite environment