This Zynq UltraScale+ RFSoC training course gives you complete overview of the architecture and capabilities of this newest Xilinx family.
This course is structured to provide designers with an overview of the hard block capabilities
for the Zynq UltraScale+ RFSoC family. Special emphasis is placed on the Data Converter and
Soft-Decision FEC blocks.
Power estimation is covered to help designers identify the power demands of the device in various operating modes. Since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device, proper layout and PCB considerations are also covered.
Power estimation is covered to help designers identify the power demands of the device in various operating modes. Since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device, proper layout and PCB considerations are also covered.
Release date
September 2018Level
Connectivity 3Training duration
2 daysPrice
USD 1800 or 18 Training CreditsCourse Part Number
CONN-RFSOC-ILTWho Should Attend?
Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ RFSoC data converter and SD-FEC hard blocks.Prerequisites
- Suggested: Understanding of the Zynq UltraScale+ MPSoC architecture
- Basic familiarity with data converter terms and principles
- Basic familiarity with forward error correction terms and principles
Software Tools
- Vivado Design Suite 2018.1
Hardware
- Host computer for running the above software
Skills gained
After completing this comprehensive training, you will have the necessary skills to:- Describe in general the new Zynq UltraScale+ RFSoC family
- Identify typical applications for the data converters
- Describe the architecture and functionality of the ADC
- Utilize the ADC via configuration, simulation, and implementation
- Describe the architecture and functionality of the DAC
- Utilize the DAC via configuration, simulation, and implementation
- Identify the requirements and options for data converter PCB designs
- Describe the architecture and functionality of the SD-FEC hard IP
- Utilize the SD-FEC via configuration, simulation, and implementation
Course Outline
- Zynq UltraScale+ RFSoC Overview {Lectures}
- RFSoC ADC {Lectures, Demo, Lab}
- RFSoC DAC {Lectures, Demo, Lab}
- RFSoC Data Converter Design {Lectures, Labs}
- PCB Design for RFSoC Devices {Lectures}
- RFSoC SD-FEC {Lectures, Demo, Lab}
Topic Descriptions
- Zynq UltraScale+ RFSoC Overview – Overview of the Zynq UltraScale+ RFSoC architecture, including brief introductions to RF, data converter solutions, SD-FEC solutions, driver support, and tool support.
- RF-ADC – Covers the basics of ADCs. Reviews ADC architecture, functionality, interfaces, configuration, and driver support.
- RF-DAC – Covers the basics of DACs. Reviews DAC architecture, functionality, interfaces, configuration, and driver support.
- Data Converter Design – Describes common features, the design flow, and utilizing the example design by simulation and implementation.
- PCB Design for RFSoC Devices – Describes power requirements, performing power estimation, and utilizing the power design. Analog signal requirements, PCB materials and layer stackup options, and analog trace design are also covered.
- Soft-Decision FEC – Covers the basics of forward error correction. Reviews SD-FEC architecture, functionality, interfaces, configuration, and driver support.
Please download the respective PDF of your course: *
* The course version can be found in the training registration form