DSP Design Using System Generator

• Implementing DSP functions using System Generator for DSP
• Utilizing design implementation tools
• Verifying through hardware co-simulation

Who Should Attend?

Prerequisites

• Experience with the MATLAB and Simulink software
• Basic understanding of sampling theory

Skills gained

• Describe the System Generator design flow for implementing DSP functions
• Identify Xilinx FPGA capabilities and implement a design from algorithm concept to hardware simulation
• List various low-level and high-level functional blocks available in System Generator
• Run hardware co-simulation
• Identify the high-level blocks available for FIR and FFT designs
• Implement multi-rate systems in System Generator
• Integrate System Generator models into the Vivado IDE
• Design a processor-controllable interface using System Generator for DSP
• Generate IPs from C-based design sources using the Vitis HLS tool for use in the System Generator environment
• Create and simulate designs using Model Composer

Course Outline

• Introduction to System Generator
• Simulink Software Basics
• Lab 1: Using the Simulink Software
• Basic Xilinx Design Capture
• Demo: System Generator Gateway Blocks
• Lab 2: Getting Started with Xilinx System Generator
• Signal Routing
• Lab 3: Signal Routing
• Implementing System Control
• Lab 4: Implementing System Control
• Multi-Rate Systems
• Lab 5: Designing a MAC-based FIR
• Filter Design
• Lab 6: Designing a FIR Filter Using the FIR Compiler Block
• System Generator, Vivado Design Suite, and Vitis HLS Integration
• Lab 7: System Generator and Vivado IDE Integration
• DSP Platforms
• Lab 8: System Generator and Vitis HLS Tool Integration
• Lab 9: AXI-4 Lite Interface Synthesis
• Introduction to Model Composer
• Demo: Introduction to Model Composer
• [OPTIONAL]: Importing C/C++ Code to Model Composer
• [OPTIONAL]: Automatic Code Generation Using Model Composer
• [OPTIONAL]: Lab 10: Model Composer and Vivado IDE Integration

Lab Descriptions

• Lab 1: Using the Simulink Software - Learn how to use Simulink toolbox blocks and design a system. Understand the effect sampling rate.
• Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
• Lab 3: Signal Routing - Design padding and unpadding logic by using signal routing blocks.
• Lab 4: Implementing System Control - Design an address generator circuit by using blocks and Mcode.
• Lab 5: Designing a MAC-based FIR - Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.
• Lab 6: Designing a FIR Filter Using the FIR Compiler Block or DAFIR Block - Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
• Lab 7: System Generator and Vivado IDE Integration - Embed System Generator models into the Vivado IDE.
• Lab 8: System Generator and Vitis HLS Tool Integration - Generate IP from a C-based design to use with System Generator.
• Lab 9: AXI4-Lite Interface Synthesis - Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq UltraScale+ MPSoC processor system. Then create and debug the application project using the Vitis IDE.
• Lab 10: Model Composer and Vivado IDE Integration - Embed a Model Composer model into the Vivado IDE.

Special Comments

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• DSP_Design_Using_System_Generator_dsp-sysgen_2020-2_ilt_H.pdf