Home
  • About Us
    • History
    • Mission
    • Team
    • Partners & Memberships
    • Customer Stories
  • Applications
    • Video
    • Automotive
    • Aerospace & Defense
    • Industrial
    • Telecommunications
  • News
    • Press Releases
    • Blog
    • Events
  • Careers
  • Contact
  • LinkedIn
  • Twitter
Xilinx & Verification Training Courses
Quality training delivered by industry experts
Back to
Course scheduleCourse list

Embedded Systems Design

Embedded systems design training that will show you how to develop systems for Xilinx Zynq SoCs & Zynq UltraScale+ MPSoCs.

Learn general embedded concepts, tools, and techniques using the Vivado Design Suite.

The emphasis is on:
  • Designing, expanding, and modifying embedded systems utilizing the features and capabilities of the Zynq® System on a Chip (SoC), Zynq UltraScale+™ MPSoC, or MicroBlaze™ soft processor
  • Adding and simulating AXI-based peripherals using bus functional model (BFM) simulation.

Release date

July 2016

Level

Embedded Hardware 3

Training duration

2 days

Price

USD 1600 or 16 Training Credits

Course Part Number

EMBD-HW

Who Should Attend?

Engineers who are interested in developing embedded systems with the Xilinx Zynq SoC, Zynq UltraScale+ MPSoC, and/or MicroBlaze soft processor core

Prerequisites

  • FPGA design experience
  • Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx Vivado software implementation tools
  • Basic understanding of C programming
  • Basic understanding of microprocessors
  • Some HDL modeling experience

Software Tools

  • Vivado Design or System Edition 2020.1
  • Vitis unified software platform 2020.1

Hardware

  • Architectures: Zynq-7000 SoC (Cortex-A9 processor), Zynq UltraScale+ MPSoC (Cortex-A53 and Cortex-R5 processors), and MicroBlaze processor
  • Demo board: Zynq UltraScale+ ZCU104 board (optional)

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Describe the various tools that encompass a Xilinx embedded design
  • Rapidly architect an embedded system containing a Cortex-A9/A53/R5 or MicroBlaze processor using the Vivado IP integrator and Customization Wizard
  • Develop software applications utilizing the Vitis unified software platform
  • Create and integrate an IP-based processing system component in the Vivado Design Suite
  • Design and add a custom AXI interface-based peripheral to the embedded processing system
  • Simulate a custom AXI interface-based peripheral using verification IP (VIP)

Course Outline

  • Embedded UltraFast Design Methodology – Outlines the different elements that comprise the Embedded Design Methodology. {Lecture, Demo}
  • Overview of Embedded Hardware Development – Overview of the embedded hardware development flow. {Lecture, Demo}
  • Driving the IP Integrator Tool – Describes how to access and effectively use the IPI tool. {Lecture, Lab}
  • Overview of Embedded Software Development – Reviews the process of building a user application.{Lecture}
  • Driving the Vitis Software Development Tool – Introduces the basic behaviors required to drive the Vitis tool to generate a debuggable C/C++ application. {Lecture, Lab}
  • AXI: Introduction – Introduces the AXI protocol. {Lecture}
  • AXI: Variations – Describes the differences and similarities among the three primary AXI variations. {Lecture}
  • AXI: Transactions – Describes different types of AXI transactions. {Lecture, Demo, Lab}
  • Introduction to Interrupts – Introduces the concept of interrupts, basic terminology, and generic implementation. {Lecture}
  • Interrupts: Hardware Architecture and Support - Reviews the hardware that is typically available to help implement and manage interrupts. {Lecture}
  • AXI: Connecting AXI IP – Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.{Lecture, Demo}
  • Creating a New AXI IP with the Wizard – Explains how to use the Create and Import Wizard to create and package an AXI IP. {Lecture, Lab}
  • AXI: BFM Simulation Using Verification IP – Describes how to perform BFM simulation using the Verification IP.(Lecture, Lab}
  • MicroBlaze Processor Architecture Overview – Overview of the MicroBlaze microprocessor architecture. {Lecture, Lab}
  • MicroBlaze Processor Block Memory Usage – Highlights how block RAM can be used with the MicroBlaze processor. {Lecture}
  • Zynq-7000 SoC Architecture Overview – Overview of the Zynq-7000 SoC architecture. {Lecture, Lab, Demo}
  • Zynq UltraScale+ MPSoC Architecture Overview – Overview of the Zynq UltraScale+ MPSoC architecture. {Lecture, Lab, Demo}

Please download the respective PDF of your course: *

  • Embedded_Systems_Design_for_FPGA_designers_embd-hw_2020-1_ilt_H.pdf

Enquire Now

* The course version can be found in the training registration form
Contact HardentContact me
Your Trainer, Reg
Have a question about the course?

Course Schedule

  • Enquire Now
Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
Upcoming Sessions
Jan 27–28
Designing with Versal AI Engine 2
Register
Feb 01–04
Introduction to UVM
Register
Feb 02–03
Designing with the Versal ACAP: Embedded Processor Architecture and Methodology
Register
Feb 03–04
Advanced Hardware Debugging Techniques Using Vivado Design Suite
Register
Complete Course Schedule
Latest News
Contact Us
Hardent Announces Availability of New Xilinx Versal ACAP Training Courses
New Xilinx Versal ACAP training courses will cover all aspects of designing with the latest Xilinx device category.
More
Hardent Announces Expansion of Xilinx Training in the USA
Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.
More
Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies
PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.
More
Upcoming Sessions
Jan 27–28
Designing with Versal AI Engine 2
Register
Feb 01–04
Introduction to UVM
Register
Feb 02–03
Designing with the Versal ACAP: Embedded Processor Architecture and Methodology
Register
Feb 03–04
Advanced Hardware Debugging Techniques Using Vivado Design Suite
Register
Complete Course Schedule
Contact Hardent
Your Trainer, Reg
Have a question about the course?
HardentMontreal
450 rue Saint-Pierre, suite 300
Montreal
,
QC
H2Y 2M9
Canada
T +1 (514) 284-5252
F +1 (514) 284-5052
Tick to hear more from Hardent by email. This includes our newsletter, details about offers, new courses, and events. You can opt out at any time. For further information, please refer to our privacy policy.

Time to market was one of our first considerations in choosing Hardent to design a PCI communication bridge. They grasped the project requirements in a matter of days. Their impressive expertise and responsiveness made the development process very smooth, as if they were working right down the hall.

Nicolas Gonthier
Hardware Design Manager
Verint Systems Canada Inc.
More testimonials
Training Partners
WHDL logo
Hardent © 2002-2021.
All rights reserved.
  • Privacy Policy
We use cookies to ensure that we give you the best experience on our website. By continuing to use this website, you consent to our use of cookies. OK