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FPGA Design with Vivado Design Suite: The Essentials 1

Learn the essentials of Xilinx FPGA design using the Vivado Design Suite flow.

This course offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those unfamiliar with the Vivado Design Suite Flow.

The course provides an introduction to Xilinx FPGA Architecture and 3D ICs, and describes how to build an effective FPGA design using the Vivado Design Suite Tools.

Release date

March 17, 2020

Level

FPGA 2

Training duration

2 days

Price

USD 1600 or 16 Training Credits

Course Part Number

HDT-FPGA1-ILT

Who Should Attend?

Digital designers new to FPGA design who need to learn the FPGA design cycle, or those who have a working knowledge of HDL (VHDL or Verilog) and seek to learn the major aspects of the Vivado Design Suite

Prerequisites

  • Basic knowledge of the VHDL or Verilog language
  • Digital design knowledge

Software Tools

  • Vivado Design or System Edition 2021.1

Hardware

  • Architecture: UltraScale™ family
  • Demo board: None

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Describe Xilinx FPGA Architecture and 3D ICs
  • Create a Vivado Design Suite project with source files using either the IDE or a Tcl script
  • Implement synchronous design techniques
  • Perform Basic Design Analysis and Design Rule Checks
  • Create pin assignments
  • Create, package and manage your own IP
  • Include your own IP into the Vivado IP catalog to reuse across multiple projects

Course Outline

  • Introduction to FPGA Architecture, 3D ICs, SoCs - Overview of FPGA architecture, SSI technology, and SoC device architecture. {Lecture}
  • Introduction to Vivado Design Flows - Introduces the Vivado design flows: the project flow and non-project batch flow. {Lecture}
  • Vivado Design Suite Project-based Flow - Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE, and simulating the design. {Lecture, Lab}
  • Basic Design Analysis in the Vivado IDE {Lab}
  • Vivado Design Rule Checks {Lab}
  • Introduction to the Tcl Environment - Introduces Tcl (tool command language). {Lecture, Lab}
  • Using Tcl Commands in the Vivado Design Suite Project Flow - Explains what Tcl commands are executed in a Vivado Design Suite project flow. {Lecture, Demo}
  • Design Analysis Using Tcl Commands - Analyze a design using Tcl commands. {Lecture, Demo, Lab}
  • Scripting in Vivado Design Suite Project Mode - Explains how to write Tcl commands in the project-based flow for a design. {Lecture, Lab}
  • Vivado Design Suite Non-Project Mode - Create a design in the Vivado Design Suite non-project mode. {Lecture}
  • Scripting in Vivado Design Suite Non-Project Mode - Write Tcl commands in the non-project batch flow for a design. {Lecture, Lab}
  • Vivado Design Suite I/O Pin Planning - Use the I/O Pin Planning layout to perform pin assignments in a design. {Lecture, Lab}
  • Vivado IP Flow - Customize IP, instantiate IP, and verify the hierarchy of your design IP. {Lecture, Demo, Lab}
  • Using an IP Container - Use a core container file as a single file representation for an IP. {Lecture, Demo}
  • Managing Remote IP - Store IP and related files remote to the current working project directory. {Lecture, Lab}
  • Creating and Packaging Custom IP - Create your own IP and package and include it in the Vivado IP catalog. {Lecture, Lab}
  • Designing with the IP Integrator - Use the Vivado IP integrator to create the uart_led subsystem. {Lecture, Demo, Lab, Case Study}
  • Manipulating Design Properties Using Tcl (Optional) - Query your design and make pin assignments by using various Tcl commands. {Lecture, Lab}

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