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Xilinx & Verification Training Courses
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FPGAs for Managers

Get an overview of the FPGA design process: FPGA project stages, project management processes, tools, and much more.

This one-day training course provides an overview of the FPGA design process for managers and non-designers working with FPGA design teams. You will learn how to identify the deliverables for the various FPGA project stages, understand the important project management processes and tools involved in the FPGA design process, and create the infrastructure for FPGA projects. Depending on individual customer requirements, the training course can also cover Xilinx products, the Vivado Design Suite, Introduction to Tcl, Introduction to XDC, or other topics.

Release date

August 11, 2016

Level

Beginner

Training duration

1 day

Price

USD 7000

Course Part Number

HDT-FPGAMNGRS-100

Who Should Attend?

Managers and non-designers working with FPGA design teams

Prerequisites

None

Software Tools

None

Hardware

None

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Understand the main concepts of the FPGA design process
  • Identify the activities, deliverables, and documentation generated at each phase of an FPGA project
  • Identify the critical members of the FPGA implementation team and understand the important project management processes and tools involved in the FPGA design process
  • Understand how to create the infrastructure for FPGA projects

Course Outline

  • Introduction to the FPGA Design Process
  • What is an FPGA project
  • What are the risks associated with FPGA design
  • What are the fundamental building blocks of FPGAs
  • How are those building blocks accessed during the normal design process
  • How the FPGA design process is NOT software
  • Digital System Project Design Process
  • Project Management
  • Implementation Guidelines
  • Final Module

Please download the respective PDF of your course: *

  • FPGAs_for_Managers_hdt-fpgamngrs-100_ilt.pdf

Enquire Now

* The course version can be found in the training registration form
Contact HardentContact me
Mary-Ann Conly
Training Coordinator

Course Schedule

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Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
Upcoming Sessions
Jan 27–28
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Feb 01–04
Introduction to UVM
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Feb 02–03
Designing with the Versal ACAP: Embedded Processor Architecture and Methodology
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Feb 03–04
Advanced Hardware Debugging Techniques Using Vivado Design Suite
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Complete Course Schedule
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Upcoming Sessions
Jan 27–28
Designing with Versal AI Engine 2
Register
Feb 01–04
Introduction to UVM
Register
Feb 02–03
Designing with the Versal ACAP: Embedded Processor Architecture and Methodology
Register
Feb 03–04
Advanced Hardware Debugging Techniques Using Vivado Design Suite
Register
Complete Course Schedule
Contact Hardent
Mary-Ann Conly
Training Coordinator
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I’ve worked with Hardent for many years and have recommended them a few times in the past. Hardent has always been extremely successful with their clients. They have many flexible ways of working with a client and will negotiate a mutually beneficial solution.

In our case, they just log into our servers and we are in constant contact via IM, email, phone, etc., but they have all their own design tools as well, so they can work either way. Being in the same time zone makes working with them easy. I am sure you will be happy with the outcome of their work. They’ll hit the ground running much faster than a single contractor would.

Marshall Johnson
Sr. Director Global ASIC/FPGA/IP Development
ADVA Optical Networking
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