This workshop introduces you to fundamental connectivity concepts and techniques for implementation in Xilinx FPGAs. The focus is on fundamental aspects of serial transceivers, PCIe technology, memory interfaces, and Ethernet MACs. Only essential theory is introduced in order to lay a foundation for the material and topics covered in this workshop, which complements more detailed training found in subsequent Xilinx courses. Design examples and labs show components from the Connectivity Targeted Reference Design (TRD). In addition, an IBERT lab is available that highlights the usage of the serial transceivers.
Release dateDecember 2013
Training duration1 day
PriceUSD 800 or 8 Training Credits
Course Part NumberCONN13000
Who Should Attend?
- FPGA designers and logic designers
- VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
- FPGA design experience or Essentials of FPGA Design course
- Basic understanding of digital and analog circuit design
- Basic understanding of high-speed serial I/O applications
- Vivado Design or System Edition 2013.2
- Architecture: 7 series FPGAs (especially the Kintex-7 FPGA)*
- Demo board: Kintex-7 FPGA KC705 board
Skills gainedAfter completing this comprehensive training, you will have the necessary skills to:
- Describe the basic functionality and usage of connectivity hard IP
- Describe the basic functionality and usage of connectivity soft IP
- Describe the basic building blocks of the Connectivity Targeted Reference Design
- Describe the main applications in the Connectivity domain
- Apply your knowledge to use and modify the Targeted Reference Designs
- Optimize serial links using the Vivado logic analyzer
- Transceiver Overview
- Lab 1: Transceiver Design
- PCI Express Technology Overview
- Lab 2: PCIe Design
- Memory Interfaces Overview
- Lab 3: MIG Design
- Ethernet MAC Overview
- Lab 4: TEMAC Design
- AXI and IP Interface Overview
- Connectivity Applications
- Lab 6: IBERT Lab
- Lab 1: Transceiver Design - Use the 7 Series FPGAs Transceiver Wizard to create a GTX transceiver IP. Optionally, download onto the development board to verify functionality.
- Lab 2: PCIe Design - Introduces the Vivado IP catalog interface for generating the PCIe block design for a Kintex-7 FPGA application. Optionally, verify functionality in a real system.
- Lab 3: Memory Interface Design - Create a DDR3 memory controller with the 7 series MIG within the Vivado IP catalog that will be used in a pre-written design. Optionally, download onto the development board to verify functionality..
- Lab 4: TEMAC Design - Use the Tri Mode Ethernet MAC IP within the Vivado IP catalog to generate an EMAC application. Optionally, verify functionality in a real system.
- Lab 6: IBERT Lab - Use the 7 series FPGAs IBERT design to verify a GTX link on the development board
Please download the respective PDF of your course: *
* The course version can be found in the training registration form