Learn the more advanced Vivado Design Suite flows in this 2-day intermediate training.
This course offers intermediate training on the Vivado® Design Suite and demonstrates the FPGA design flow for those wanting to go beyond the basics and learn the more advanced Vivado Design Suite flows.
Release date
April 22, 2020Level
FPGA 3Training duration
2 daysPrice
USD 1600 or 16 Training CreditsCourse Part Number
HDT-VDESP-ILTWho Should Attend?
Digital designers who want to increase their exposure of the Vivado FPGA design Suite, or those who have a working knowledge of HDL (VHDL or Verilog) and seek to increase their productivity using more of the major aspects of the Vivado Design SuitePrerequisites
- Basic knowledge of the VHDL or Verilog language
- Digital design experience
- FPGA Design with Vivado Design Suite: The Essentials
Software Tools
- Vivado Design or System Edition 2020.1
Hardware
- Architecture: UltraScale™ family
- Demo board: None
Skills gained
After completing this comprehensive training, you will have the necessary skills to:- Simulate, synthesize, and implement a design
- Identify advanced FPGA configurations, such as daisy chains and gangs, for configuring multiple FPGAs in a design
- Utilize Xilinx security features, bitstream encryption, and authentication using AES for design and IP security
- Use some of the more prominent design wizards
- Implement synchronous design techniques
- Use Xilinx FPGA power estimation tools throughout the design cycle
- Utilize floorplanning techniques to improve design performance
- Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
Course Outline
- Behavioral Simulation - Describes the process of behavioral simulation and the simulation options available in the Vivado® IDE. {Lecture}
- Timing Simulation - Simulate the design post-implementation to verify that a design works properly on hardware. {Lecture, Lab}
- Vivado Synthesis and Implementation - Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board. {Lecture, Lab}
- Introduction to FPGA Configuration - Describes how FPGAs can be configured. {Lecture}
- Configuration Process - Understand the FPGA configuration process, such as device power up, CRC check, etc. {Lecture}
- Configuration Modes - Understand various configuration modes and select the suitable mode for a design. {Lecture}
- Bitstream Security - Understand the Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication. {Lecture, Demo}
- Timing Constraints Wizard - Use the Timing Constraints Wizard to apply missing timing constraints in a design. {Lecture, Lab}
- Timing Constraints Editor - Introduces the timing constraints editor tool to create timing constraints. {Lecture}
- Synchronous Design Techniques - Introduces synchronous design techniques used in an FPGA design. {Lecture}
- Register Duplication - Use register duplication to reduce high fanout nets in a design. {Lecture}
- Pipelining - Use pipelining to improve design performance. {Lecture}
- Timing Summary Report - Use the post-implementation timing summary report to sign-off criteria for timing closure. {Lecture, Demo}
- Baselining - Use Xilinx-recommended baselining procedures to progressively meet timing closure. {Lecture, Demo}
- Xilinx Power Estimator Spreadsheet - Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. {Lecture, Lab}
- Power Analysis and Optimization Using the Vivado Design Suite - Use report power commands to estimate power consumption. {Lecture, Lab}
- Dynamic Power Estimation Using Vivado Report Power - Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design. {Lecture}
- Power Management Techniques - Identify techniques used for low power design. {Lecture}
- Revision Control Systems in the Vivado Design Suite - Use version control systems with Vivado design flows. {Lecture, Lab}
- Hierarchical Design - Describe and analyze the hierarchical design methodologies supported by the Vivado Design Suite {Lecture}
- Floorplanning - How to utilize floorplanning techniques to improve design performance {Lecture}
- Physical Optimization - Employ physical optimization techniques to aid in timing closure {Lecture}
- Incremental Design - Investigate re-entrant mode as a last mile strategy {Lecture, Lab}
Please download the respective PDF of your course: *
* The course version can be found in the training registration form