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Introduction to Signal Integrity for Xilinx FPGAs

Get a complete introduction to Signal Integrity for Xilinx FPGA designs in 1 day.

Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This introductory course combines analysis techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.

You will work with IBIS models and witness simulations using Mentor Graphics HyperLynx. This course balances lecture modules with instructor demonstrations.

Release date

April 2020

Level

Connectivity 3

Training duration

1 day

Price

USD 800 or 8 Training Credits

Course Part Number

CONN-INTROSI-ILT

Who Should Attend?

Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users of Xilinx products who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.

Prerequisites

  • Familiarity with high-speed PCB concepts
  • Basic knowledge of digital and analog circuit design

Software Tools

  • None required

Hardware

  • Architecture: N/A
  • Demo board: None

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Describe signal integrity effects
  • Predict and overcome signal integrity challenges
  • Simulate signal integrity effects
  • Verify and derive design rules for the board design
  • Apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and semiconductor circuits

Course Outline

  • Signal Integrity Introduction
  • Transmission Lines
  • IBIS Models and SI Tools
  • Demo: Retrieving Xilinx IBIS Models
  • Reflections
  • Demo: Using HyperLynx
  • Crosstalk
  • Signal Integrity Analysis
  • Power Supply Issues
  • Signal Integrity Summary

Special Comments

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