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Introduction to the Zynq All Programmable SoC Architecture

This course provides hardware and firmware engineers with the knowledge to effectively utilize a Zynq All Programmable System on a Chip (SoC). It covers the architecture of the ARM Cortex-A9 processor-based processing system (PS) and the integration of programmable logic (PL).

The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.
Release date
August 2016
Level
Embedded Hardware and Firmware 3
Training duration
1 day
Price
USD 800 or 8 Training Credits
Course Part Number
EMBD-INTROZARCH
Who Should Attend?
Hardware and firmware engineers who are interested in implementing a system on a chip using the Zynq All Programmable SoC and programmable logic.
Prerequisites
  • FPGA design experience
  • Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx ISE software implementation tools
  • Basic understanding of C programming
  • Basic understanding of microprocessors
  • Some HDL modeling experience
Software Tools
  • Vivado Design or System Edition 2017.3
Hardware
  • Architecture: Zynq-7000 All Programmable SoC
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard
Skills gained
After completing this comprehensive training, you will have the necessary skills to:
  • Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)
  • Evaluate a processing system (PS) and programmable logic (PL) AXI interface
  • Identify the configuration options for the Zynq All Programmable SoC
Course Outline
  • Zynq All Programmable SoC Overview {Lecture, Demo}
  • Zynq All Programmable SoC Application Processor Unit (APU) {Lecture, Lab}
  • Zynq All Programmable SoC Processor Input/Output Peripherals {Lecture, Demo}
  • Zynq All Programmable SoC PS-PL Interface {Lecture, Demo, Lab}
  • Zynq All Programmable SoC Booting {Lecture, Lab}
  • Zynq All Programmable SoC Memory Resources {Lecture, Demo}
Topic Descriptions
  • Zynq All Programmable SoC Overview {Lecture, Demo} – Provides a general overview of the Zynq All Programmable SoC.
  • Zynq All Programmable SoC Application Processor Unit (APU) {Lecture, Lab} – Explores the individual components that comprise the APU.
  • Zynq All Programmable SoC Processor Input/Output Peripherals {Lecture, Demo} – Introduces the components that comprise the IOP block of the Zynq device PS.
  • Zynq All Programmable SoC PS-PL Interface {Lecture, Demo, Lab} – Describes in detail the PS interconnect and how it affects PL architecture decisions.
  • Zynq All Programmable SoC Booting {Lecture, Lab} – Explains the boot process of the PC and configuration of the PL.
  • Zynq All Programmable SoC Memory Resources {Lecture, Demo} – Explains the operation of the on-chip (OCM) memory and various memory controllers located in the PS.
Special Comments

Pre-Register

* The course version can be found in the training registration form