This training course will prepare you to migrate from Spartan-6 to a new Xilinx device family.
This course offers an overview of key points of consideration and specific guidance in migrating a Spartan-6® FPGA design to a newer Xilinx target technology. The training focuses on migration to Xilinx 28nm and 16nm architectures, as well as key differences between ISE® Design Suite and Vivado® ML. Topics covered will include software flow, utilization of IP, constraining the design in the target architecture, and much more.
Release date
November 2021Level
FPGA 2Training duration
1 dayPrice
USD 800 or 8 Training CreditsCourse Part Number
HDT-FPGAS6-ILTWho Should Attend?
Architects, Managers, FPGA Designers, Board Designers, and anyone considering migrating from Spartan-6 FPGAs to a newer Xilinx architecturePrerequisites
- Basic FPGA architecture understanding
- Basic Xilinx design flow understanding
Software Tools
- Vivado ML 2021.1
Hardware
- Architecture: Spartan-6, UltraScale™ and 7 series FPGAs
- Demo board: None
Skills gained
After completing this comprehensive training, you will have the necessary skills to:- Review an existing Spartan-6 design with system requirements in hand and know how to begin, progress, and close the design in the new target technology.
- Understand key differences in constraining the technologies, migrating IP, driving and directing the stages of the different tools involved, etc., leading to a better design migration experience.
Course Outline
- Introduction
- Architecture Comparison
- ISE to Vivado ML Overview
- Constraints
- Constraints Editor
- Lab: Intro to Timing Exceptions
- Intellectual Property
- Lab: Vivado IP Flow
- Inputs and Outputs
- Lab: Vivado IO Pin Planning
- Vivado Reports
- Design Migration and Baselining