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Migrating from Spartan-6

This training course will prepare you to migrate from Spartan-6 to a new Xilinx device family.

This course offers an overview of key points of consideration and specific guidance in migrating a Spartan-6® FPGA design to a newer Xilinx target technology. The training focuses on migration to Xilinx 28nm and 16nm architectures, as well as key differences between ISE® Design Suite and Vivado® ML. Topics covered will include software flow, utilization of IP, constraining the design in the target architecture, and much more.

Release date

November 2021

Level

FPGA 2

Training duration

1 day

Price

USD 800 or 8 Training Credits

Course Part Number

HDT-FPGAS6-ILT

Who Should Attend?

Architects, Managers, FPGA Designers, Board Designers, and anyone considering migrating from Spartan-6 FPGAs to a newer Xilinx architecture

Prerequisites

  • Basic FPGA architecture understanding
  • Basic Xilinx design flow understanding

Software Tools

  • Vivado ML 2021.1

Hardware

  • Architecture: Spartan-6, UltraScale™ and 7 series FPGAs
  • Demo board: None

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Review an existing Spartan-6 design with system requirements in hand and know how to begin, progress, and close the design in the new target technology.
  • Understand key differences in constraining the technologies, migrating IP, driving and directing the stages of the different tools involved, etc., leading to a better design migration experience.

Course Outline

  • Introduction
  • Architecture Comparison
  • ISE to Vivado ML Overview
  • Constraints
  • Constraints Editor
    • Lab: Intro to Timing Exceptions
  • Intellectual Property
    • Lab: Vivado IP Flow
  • Inputs and Outputs
    • Lab: Vivado IO Pin Planning
  • Vivado Reports
  • Design Migration and Baselining

Special Comments

Please download the respective PDF of your course: *

  • Migrating_From_Spartan-6_hdt-fpgas6_2021-1_ilt_H.pdf

Enquire Now

Related Courses

FPGA Design with Vivado Design Suite: The Essentials 2

View course

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

View course

Advanced Timing Closure Techniques for the Vivado Design Suite

View course
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Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
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