This course introduces designers to the basic concepts of 7 Series FPGAs, specifically on how to efficiently utilize CLB architecture, Memory resources and DSP resources in their designs. Modules associated with the individual resources are immediately followed by a lab exercise.The course starts with an overview of the 7 Series FPGA families and then, details the architectural features of the devices.
Release dateNovember 2012
Training duration5-8 hours (available online for 30 days)
PriceUSD 500 or 5 Training Credits
Course Part Number7S-20000
Who Should Attend?Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
- Essentials of FPGA Design (v14.1 or earlier)
- Intermediate VHDL or Verilog knowledge
- Xilinx ISE® Design Suite v14.1
Skills gainedAfter completing this comprehensive training, you will have the necessary skills to:
- Describe the functionality of the 6-input LUT and the CLB construction of the 7 Series FPGAs
- Specify the CLB resources and the available slice configurations for the 7 Series FPGAs
- Define the block RAM, FIFO, and DSP resources available for the 7 Series FPGAs
- Properly design for the I/O block and SERDES resources in the 7 Series FPGAs
- 7 Series FPGA Overview
- CLB Architecture
- Slice Flip-Flops
- Lab 1: CLB Resources
- Memory Resources
- Lab 2: Memory Resources
- DSP Resources
- Lab 3: DSP Resources
- Lab 1: CLB Resources - Complete the code for a 32-bit counter design and use the RTL technologies schematic viewers and FPGA editor to examine the design after various steps in the implication process.
- Lab 2: Memory Resources - Complete the code for a read-first, true dual-port memory; use the schematic viewers and FPGA editor to analyze the design at various stages; modify the code to implement a write-first memory and finally, infer a true dual-port block RAM in both read-first and write-first modes.
- Lab 3: DSP Resources - Complete the code for a 24 by 17 bit multiply accumulate design; use the FPGA editor to view the design after different steps in the implementation process; create a wide pipeline multiplier, instantiate it in your design and analyze the resulting structure.
Special CommentsThis course is a shorter version of the 2-day Designing with the Xilinx 7 Series Families.
Please download the respective PDF of your course: *
* The course version can be found in the training registration form