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Introduction to UVM Universal Verification Methodology (On-Demand)

This online UVM training offers self-paced learning combined with practical lab exercises. You will learn how to construct your own UVM testbench and get a certificate of completion.

This on-demand video course introduces engineers to UVM (Universal Verification Methodology), the exciting open-source library that has quickly become the reference verification methodology for the electronic design community. The course teaches you the key base classes in the library and how to use them. You will learn about the structure of a UVM testbench, the core components required for a working testbench, and how to use TLM communication between the components of your testbench. You will see how to create transactor classes like drivers and monitors and analysis components like scoreboards and coverage collectors. You will learn the best strategies for connecting your UVM testbench to the RTL DUT. Other library features you will learn to deploy are factory creation and overrides, environment customization using configuration objects, scalable stimulus generation with sequences, and how to design your testbench for reuse.

The labs require that you have access to a supported SystemVerilog simulator running on a Linux platform. Please note, we do not support the Windows platform. The lab files we supply with this course support the top three simulators: Questa from Mentor Graphics, VCS from Synopsys, and XCelium from Cadence Design Systems. A makefile is provided that may be used to invoke the simulator of your choice.

As a special introductory offer, you also get access to three follow-on online group Q and A sessions with a verification expert. This offer is available for a limited time only. Sessions are scheduled once a month, and students must sign up in advance to attend a session.

Release date

19 Nov, 2013

Level

UVM 1

Training duration

12-14 hours (available online for 30 days)

Price

USD 1200

Course Part Number

WHDL-UVM-ODV

Who Should Attend?

Engineers interested in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM) library.

Prerequisites

  • Introduction to SystemVerilog course or equivalent experience writing object-oriented SystemVerilog verification code.

Software Tools

  • Simulator (provided by student)

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Explain existing UVM-based verification projects
  • Construct your own UVM testbenches
  • Create standard components like test, environment, scoreboard, agent, transactors, etc.
  • Define your own transaction Item classes
  • Use polymorphic construction techniques (factory pattern) for components and transaction objects
  • Define and distribute configuration objects for environment customization
  • Use sequences for stimulus generation

Course Outline

  • Topic 1 – Introduction
  • Topic 2 – Messaging
  • Topic 3 – TLM Communication
  • Topic 4 – Transactions
  • Topic 4 Lab – Transactions
  • Topic 5 – Components
  • Topic 6 – Component Phasing
  • Topic 6 Lab – Components
  • Topic 7 – Creating with the Factory
  • Topic 8 – Running (and Stopping) a Simulation
  • Topic 8 Lab – Environment
  • Topic 9 – Connecting to the DUT
  • Topic 10 – Sequences Part 1
  • Topic 11 – Sequences Part 2
  • Topic 11 Lab – Sequences
  • Topic 12 – Analysis
  • Topic 13 – Analysis Scoreboards
  • Topic 13 Lab – Analysis
  • Topic 14 – Hierarchy
  • Topic 14 Lab – Hierarchy
  • Topic 15 – Configurability
  • Topic 15 Lab – Factory Overrides
  • Topic 16 – Configuration Object
  • Topic 17 – Configuration Database
  • Topic 17 Lab – Configuration
  • Topic 18 – Sequence-Sequencer Connection
  • Topic 19 – Sequence Modularity
  • Topic 20 – Responses
  • Topic 20 Lab – Responses

Special Comments

Price includes shipping of course materials within North America. For shipping outside of North America, additional fees may apply.

* The course version can be found in the training registration form