Course Archive - Page 2 of 2

SystemVerilog for Design

Hardent Announces Expansion of Xilinx Training in the USA

Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.

Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies

PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.

Hardent Becomes Authorized Microchip Design Partner

FPGA design services and support from Hardent will enable Microchip customers to get their products to market more quickly.

Upcoming Sessions

Jan 26

Designing with the Versal ACAP: Network on Chip

Jan 26–28

Designing with the Zynq UltraScale+ RFSoC

Jan 26–28

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Jan 27–28

Designing with Versal AI Engine 2

Complete Course Schedule

Your trainer, Tim

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