Course Archive - Page 2 of 2

Visually lossless compression down to 6 bits per pixel

Essentials of FPGA Design (Vivado)

Hardent & Xilinx Collaborate to Deliver Complete 8K Ready DisplayPort 1.4 IP Subsystem

New IP solution combining Hardent and Xilinx IP will enable pro A/V designers to take advantage of the full DisplayPort 1.4 feature set to support resolutions up to 8K.

FPGA Design Analysis Using the Vivado Design Suite

Useful commands for FPGA design analysis in the Vivado Design Suite that will help you save time and meet your performance goals!

Hardent & WHDL Named PSS Training Provider For Breker Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Upcoming Sessions

Jul 08–11

Introduction to Universal Verification Methodology (UVM)

Jul 08–11

SystemVerilog for Verification

Jul 08–09

C-based Design - High-Level Synthesis with the Vivado HLx Tool

Jul 08–09

C-based Design - High-Level Synthesis with the Vivado HLx Tool

Complete Course Schedule

Have a question?

Ask your trainer Reg

Linked-in

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

First Name

Last Name

Title

Company

Phone

City

Country

Subject

Tick to hear more from Hardent by email. This includes our newsletter, details about offers, new courses, and events. You can opt out at any time. For further information, please refer to our privacy policy.