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Xilinx & Verification Training Courses
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PCIe Protocol Overview

This course focuses on the fundamentals of the PCI Express® protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed. Implementation issues are covered in the two-day Designing a LogiCORE PCI Express System course.

Release date

April 2011

Level

Connectivity 2

Training duration

1 day

Price

USD 800 or 8 Training Credits

Course Part Number

PCIE18000

Who Should Attend?

  • FPGA designers, logic designers, and anyone who needs an in-depth knowledge of the PCIe protocol

Prerequisites

  • None

Software Tools

  • None required
  • VCD viewer optional

Hardware

  • Architecture: N/A
  • Demo board: None

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Interpret various transactions occurring on the link
  • Describe the layered architecture and the tasks and packet types each is responsible for
  • Properly estimate maximum performance of a link
  • Illustrate how errors can be communicated within the system
  • Explain the relationship between Virtual Channels (VCs) and Traffic Class (TC) and the interaction with flow control credits

Course Outline

  • Introduction
  • Introduction to the PCIe Architecture
  • Review of the PCIe Protocol
  • Packet Formatting Details
  • Lab 1: Packet Decoding
  • Packet Routing
  • Interrupts and Error Management
  • Summary

Lab Descriptions

  • Lab 1: Packet Decoding – This lab explores what really happens on the link between a root complex and the endpoint. Various packets, including the Physical Layer, Data Link Layer, and Transaction Layer packets are explored. Insight as to what is actually transpiring on the lanes becomes a powerful tool for understanding the protocol as well as debugging various link issues.

Special Comments

Please download the respective PDF of your course: *

  • PCIe_Protocol_Overview_pcie18000_131_ilt_H.pdf

Enquire Now

Contact HardentContact me
Mary-Ann Conly
Training Coordinator

Course Schedule

  • Enquire Now
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Apr 20–22
Embedded System Design for the Zynq UltraScale+ MPSoC
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Apr 26–29
Introduction to UVM
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Apr 26–27
Embedded Design with PetaLinux Tools
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Apr 27–28
Designing with Xilinx Serial Transceivers
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Complete Course Schedule
Contact Hardent
Mary-Ann Conly
Training Coordinator
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Time to market was one of our first considerations in choosing Hardent to design a PCI communication bridge. They grasped the project requirements in a matter of days. Their impressive expertise and responsiveness made the development process very smooth, as if they were working right down the hall.

Nicolas Gonthier
Hardware Design Manager
Verint Systems Canada Inc.
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