SystemVerilog for Design

This course is aimed at RTL designers who wish to learn about the new features of SystemVerilog for RTL design. It is 2 days long, with an optional Verilog for Design precursor day for 3 days total. The student will learn about the new constructs and features in SystemVerilog designed to capture design intent to allow Simulation tools to analyze for correct RTL design practices and speed up the design process. A lab is included. Synthesis tools are not required. Most of day 2 is devoted to SystemVerilog Assertions (SVA), with practical lab exercises to reinforce the material. The optional pre-cursor day is a Verilog for Design review. It is appropriate for either VHDL RTL engineers who will be using SystemVerilog for design or Verilog engineers who want or need a review of Verilog for design. It covers basic Verilog constructs and programming for RTL synthesis. There are several labs.

Design engineers with Verilog experience who are interested in applying the synthesizable features of SystemVerilog and SystemVerilog Assertions to their designs.

After completing this comprehensive training, you will have the necessary skills to:

• Evaluate the new RTL features in SystemVerilog and what they can bring to your design methodology
• Describe the new SystemVerilog features capable of capturing the designers intent in their RTL code
• Explain how assertions can help you in your design or verification code
• Describe and deploy the most useful SVA constructs
• Write a broad range of SystemVerilog Assertions
• Use the bind directive to incorporate Assertions into design code at runtime