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SystemVerilog for Design

SystemVerilog for design training course for anyone interested in applying the synthesizable features of SystemVerilog and SystemVerilog assertions to their designs.

This course is aimed at RTL designers who wish to learn about the new features of SystemVerilog for RTL design. It is 2 days long, with an optional Verilog for Design precursor day for 3 days total. The student will learn about the new constructs and features in SystemVerilog designed to capture design intent to allow Simulation tools to analyze for correct RTL design practices and speed up the design process. A lab is included. Synthesis tools are not required. Most of day 2 is devoted to SystemVerilog Assertions (SVA), with practical lab exercises to reinforce the material. The optional pre-cursor day is a Verilog for Design review. It is appropriate for either VHDL RTL engineers who will be using SystemVerilog for design or Verilog engineers who want or need a review of Verilog for design. It covers basic Verilog constructs and programming for RTL synthesis. There are several labs.

Release date

June 27, 2016

Level

1

Training duration

2 or 3 days

Price

USD 2400 or 24 Training Credits

Course Part Number

WHDL-SYSVERDE-100

Who Should Attend?

Design engineers with Verilog experience who are interested in applying the synthesizable features of SystemVerilog and SystemVerilog Assertions to their designs.

Prerequisites

  • Strong familiarity with Verilog for RTL Design

Software Tools

  • Questa Simulator 10.4c

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Evaluate the new RTL features in SystemVerilog and what they can bring to your design methodology
  • Describe the new SystemVerilog features capable of capturing the designers intent in their RTL code
  • Explain how assertions can help you in your design or verification code
  • Describe and deploy the most useful SVA constructs
  • Write a broad range of SystemVerilog Assertions
  • Use the bind directive to incorporate Assertions into design code at runtime

Course Outline

  • Data Types - User-defined types
  • Data Types - Enumeration
  • Data Types - Casting
  • Data Types - Parameterized types
  • Tasks and Functions - SV features
  • Arrays and Structures - Packed arrays
  • Arrays and Structures - Unpacked arrays
  • Arrays and Structures - Structures
  • Arrays and Structures - Unions
  • Reducing RTL Ambiguity - always derivatives
  • RTL Programming - Operators
  • RTL Programming - Loop statements
  • RTL Programming - Decision statements
  • RTL Programming - case/if..else modifiers
  • Hierarchy - Ports
  • Hierarchy - Implicit port connections
  • Hierarchy - Packages
  • Miscellaneous Synthesizeable Constructs
  • Interfaces - Signal style
  • Interfaces - Interface as a port type
  • Interfaces - Modports
  • Interfaces - BFM style
  • SVA
  • Immediate Assertions
  • Concurrent Assertions
  • Concurrent Assertion Basics - Boolean expressions
  • Concurrent Assertion Basics - Sequences
  • Concurrent Assertion Basics - Properties
  • Concurrent Assertion Basics - Verification directives
  • Sequence Blocks - Sequence operators
  • Sequence Blocks - Sequence methods
  • Property Blocks
  • Local Data Values
  • Verification Directives - Bind directive
  • Clocks
  • Optional day: Structure
  • Optional day: Data Types
  • Optional day: Modules
  • Optional day: Hierarchy
  • Optional day: Procedural Blocks
  • Optional day: Procedural Assignments
  • Optional day: if-else and case
  • Optional day: Continuous Assignments
  • Optional day: Tasks and Functions
  • Finite State Machines

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