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SystemVerilog for Design

SystemVerilog for design training course for anyone interested in applying the synthesizable features of SystemVerilog and SystemVerilog assertions to their designs.

This course is aimed at RTL designers who wish to learn about the new features of SystemVerilog for RTL design.

The course begins with a Verilog for Design review. It is appropriate for either VHDL RTL engineers who will be using SystemVerilog for design or Verilog engineers who want or need a review of Verilog for design. It covers basic Verilog constructs and programming for RTL synthesis. The student will then learn about the new constructs and features in SystemVerilog. These are designed to capture design intent which allows Simulation tools to analyze for correct RTL design practices and speed up the design process. The final part of the course is devoted to SystemVerilog Assertions (SVA).

Practical lab exercises are included throughout the course to reinforce the material.

Release date

June 27, 2016

Level

1

Training duration

3 days

Price

USD 2400 or 24 Training Credits

Course Part Number

WHDL-SVD-100

Who Should Attend?

Design engineers with Verilog experience who are interested in applying the synthesizable features of SystemVerilog and SystemVerilog Assertions to their designs.

Prerequisites

  • Strong familiarity with Verilog for RTL Design

Software Tools

  • Questa Simulator 10.4c

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Evaluate the new RTL features in SystemVerilog and what they can bring to your design methodology
  • Describe the new SystemVerilog features capable of capturing the designers intent in their RTL code
  • Explain how assertions can help you in your design or verification code
  • Describe and deploy the most useful SVA constructs
  • Write a broad range of SystemVerilog Assertions
  • Use the bind directive to incorporate Assertions into design code at runtime

Course Outline

  • Day 1: Verilog for Design Review
    • Structure
    • Data Types
    • Modules
    • Hierarchy
    • Procedural Blocks
    • Procedural Assignments
    • if-else and case
    • Lab - case
    • Continuous Assignments
    • Tasks and Functions
    • Lab - Function
    • Finite State Machines
  • Day 2: SystemVerilog for Design
    • Data Types
      • User-defined types
      • Enumeration
      • Casting
      • Parameterized types
    • Tasks and Functions
      • SV features
    • Arrays and Structures
      • Packed arrays
      • Unpacked arrays
      • Structures
      • Unions
    • Reducing RTL Ambiguity
      • always derivatives
      • Lab - FSM
    • RTL Programming
      • Operators
      • Loop statements
      • Decision statements
      • case/if..else modifiers
    • Hierarchy
      • Ports
      • Implicit port connections
      • Packages
    • Miscellaneous Synthesizeable Constructs
      • Lab - SV UART
    • Interfaces
      • Signal style
      • Interface as a port type
      • Modports
      • BFM style
  • Day 3: SVA
    • Concurrent Assertion Basics
    • Lab – Assertion Basics
    • Boolean Expressions
    • Sequences
    • Lab – Sequences
    • Lab – Data Values
    • Properties
    • Verification Directives
    • Lab - Bind

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Related Courses

Verilog for Design

View course

SystemVerilog Assertions

View course
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