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SystemVerilog for Design

SVD 1

This 2-day course is aimed at RTL designers who wish to learn about the new features of SystemVerilog for RTL design. The student will learn about the new constructs and features in SystemVerilog that are designed to capture design intent so that Simulation tools may analyze for correct RTL design practices and speed up the design process. Day 1 does not feature labs, and no synthesis tools are required. Day 2 is devoted to SystemVerilog Assertions with practical lab exercises to reinforce the material.
Release date
June 27, 2016
Level
1
Training duration
2 days
Price
USD 1600 or 16 Training Credits
Course Part Number
WHDL-SYSVERDE-100
Who Should Attend?
Design engineers with Verilog experience who are interested in applying the synthesizable features of SystemVerilog and SystemVerilog Assertions to their designs.
Prerequisites
  • Strong familiarity with Verilog for RTL Design
Software Tools
  • Questa Simulator 10.4c
Skills gained
After completing this comprehensive training, you will have the necessary skills to:
  • Evaluate the new RTL features in SystemVerilog and what they can bring to your design methodology
  • Describe the new SystemVerilog features capable of capturing the designers intent in their RTL code
  • Explain how assertions can help you in your design or verification code
  • Describe and deploy the most useful SVA constructs
  • Write a broad range of SystemVerilog Assertions
  • Use the bind directive to incorporate Assertions into design code at runtime
Course Outline
  • Introduction
  • SystemVerilog Design
  • Data Types
  • User-defined types
  • Enumeration
  • Casting
  • Parameterized types
  • Arrays and Structures
  • Vectors, Packed arrays
  • Arrays
  • Array literals
  • Array query functions
  • Structures and Unions
  • Reducing RTL ambiguity
  • always derivatives
  • case/if..else modifiers
  • RTL Programming
  • Operators
  • Loop statements
  • Decision statements
  • SystemVerilog Assertions
  • Immediate/Concurrent
  • Severity system tasks
  • SystemVerilog Event Scheduler
  • Concurrent Assertions
  • Boolean expressions
  • System Functions
  • Sequence Blocks
  • Sequence Operators
  • Repetition
  • Non-Consecutive Repetition
  • Goto Repetition
  • Value Change Functions
  • Relating sequences
  • Sequence expressions: and, or, intersect
  • Sequence expressions
  • throughout, within, .ended
  • Sequence controls
  • Data-use within a sequence
  • Property block
  • Implication |-> |=>
  • Sequential antecedents
  • Multi-clock support
  • Verification directives
  • Clock inference and specification
  • Controlling Assertions
Please download the respective PDF of your course: *

Pre-Register

* The course version can be found in the training registration form