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TLM 2.0

Get an introduction to the TLM 2.0 modeling standard with this workshop-style training course.

This 2-day workshop introduces the student to the IEEE 1666-2012 TLM 2.0 modeling standard. It is intended for engineers who are familiar with SystemC, with an interest in learning the TLM 2.0 modeling constructs and coding styles. The student will learn how to write models that conform to the TLM2.0 standard, using both the Loosely-Timed (LT) and Approximately-timed (AT) coding styles, and offering additional features such as Direct-Memory (DMI), Debug access, and payload extensions. This course is mixed lecture and exercises, with an exercise for nearly every topic.

Release date

July 13, 2016

Level

1

Training duration

2 days

Price

USD 1600 or 16 Training Credits

Course Part Number

HDT-TLM20-100

Who Should Attend?

Engineers with SystemC experience who want to write ultra-high performance SOC models of memory-mapped systems.

Prerequisites

  • Introduction to SystemC course, or a strong knowledge of SystemC

Software Tools

  • Questa Simulator 10.4c

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Write ultra-high performance transaction-level models suitable for executing system firmware and RTOS code
  • Write models using Untimed (UT), Loosely-timed (LT) and Approximately-timed (AT) levels of abstraction as defined in the IEEE TLM-2.0 standard
  • Explain timing fidelity versus performance in order to develop the most efficient model appropriate to your needs

Course Outline

  • TLM 2.0 Overview
  • Interface Functions
  • Sockets
  • Generic Payload
  • Protocol
  • Interfaces
  • Transport
  • DMI
  • Debug
  • Sockets
  • Initiator and Target
  • Socket Binding
  • Hierarchy, Multi-connect
  • Topology Examples
  • Generic Payload Overview
  • Attributes
  • LT Coding style (and exercise)
  • Transport Interface
  • Temporal Decoupling
  • Quantum Keeper
  • AT Coding Style (and exercise)
  • Protocol Phases
  • Forward, Backward, and Return Paths
  • Base Protocol (2-phase)
  • Payload Event Queue (PEQ)
  • DMI interface
  • DMI Hint
  • DMI Data Structure
  • Invalidating DMI
  • Debug Interface (and exercise)
  • Debug Transport Interface
  • Convenience Sockets (and exercise)
  • Simple Sockets
  • Tagged Sockets
  • Multi-Passthrough Sockets
  • Generic Payload In-depth
  • Byte Enable
  • Streaming
  • Endianness
  • Memory Management
  • Generic Payload Extensions (and exercise)
  • Base Protocol In-depth
  • 4-state and Variants

Please download the respective PDF of your course: *

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* The course version can be found in the training registration form