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UltraFast Design Methodology

This course describes the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast design methodology case study. The UltraFast design methodology checklist is also introduced.
Release date
June 2016
Level
FPGA 3
Training duration
2 days
Price
USD 800 or 8 Training Credits
Course Part Number
FPGA-VDM
Who Should Attend?
Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.
Prerequisites
  • Some knowledge of FPGA design techniques is helpful
  • Experience with the Vivado Design Suite or attendance of one of our existing Vivado Design Suite training courses is required
  • Intermediate knowledge of Verilog or VHDL
Software Tools
  • Vivado Design or System Edition 2017.1
Hardware
  • Architecture: UltraScale and 7 series FPGAs
  • Demo board: None
Skills gained
After completing this comprehensive training, you will have the necessary skills to:
  • Describe the UltraFast design methodology checklist
  • Identify key areas to optimize your design to meet your design goals and performance objectives
  • Define a properly constrained design
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
  • Build resets into your system for optimum reliability and design speed
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Identify timing closure techniques using the Vivado Design Suite
  • Describe how the UltraFast design methodology techniques work effectively through case studies and lab experience
Course Outline
  • UltraFast Design Methodology: Planning {Lecture, Demo}
  • UltraFast Design Methodology: Design Creation and Analysis {Lecture}
  • HDL Coding Techniques {Lecture}
  • Resets {Lecture, Lab}
  • Register Duplication {Lecture}
  • Synchronous Design Techniques {Lecture}
  • Vivado Design Suite I/O Pin Planning {Lecture, Lab}
  • Vivado Design Rule Checks {Lab}
  • Creating and Packaging Custom IP {Lecture, Lab}
  • UltraFast Design Methodology: Design Closure {Lecture}
  • UltraFast Design Methodology: Advanced Techniques {Lecture}
  • Baselining {Lecture, Lab, Demo}
  • Pipelining {Lecture, Lab}
  • Inference {Lecture, Lab}
  • Revision Control Systems in the Vivado Design Suite {Lecture, Lab}
  • Synchronization Circuits {Lecture, Lab, Case Study}
  • Introduction to Floorplanning {Lecture}
  • Physical Optimization {Lecture, Lab}
  • Power Management Techniques {Lecture}
  • Vivado Design Suite Debug Methodology {Lecture}
Special Comments
Please download the respective PDF of your course: *

* The course version can be found in the training registration form