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UltraFast Design Methodology

Learn how to improve design speed and reliability by using the UltraFast Design Methodology and the Vivado® Design Suite.

The focus is on:
  • Optimizing system reset design and synchronization circuits
  • Employing best practice HDL coding techniques
  • Applying appropriate timing closure techniques
  • Reviewing an UltraFast Design Methodology case study

Release date

June 2016

Level

FPGA 3

Training duration

2 days

Price

USD 1600 or 16 Training Credits

Course Part Number

FPGA-VDM

Who Should Attend?

Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.

Prerequisites

  • Basic HDL knowledge (VHDL or Verilog)
  • Digital design knowledge and experience

Software Tools

  • Vivado Design Suite 2021.2

Hardware

  • Architecture: UltraScale™ FPGAs
  • Demo board: None

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Describe the UltraFast design methodology checklist
  • Identify key areas to optimize your design to meet your design goals and performance objectives
  • Define a properly constrained design
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
  • Build resets into your system for optimum reliability and design speed
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Identify timing closure techniques using the Vivado Design Suite
  • Describe how the UltraFast design methodology techniques work effectively through case studies and lab experience

Course Outline

  • Ultra Fast Design Methodology
    • UltraFast Design Methodology: Introduction - Introduces the UltraFast Design Methodology and the UltraFast Design Methodology checklist. {Lecture, Demo}
    • UltraFast Design Methodology: Board and Device Planning - Introduces the methodology guidelines on board and device planning.{Lecture}
    • UltraFast Design Methodology: Design Creation - Introduces the UltraFast methodology guidelines on design creation. {Lecture}
    • UltraFast Design Methodology: Implementation - Introduces the methodology guidelines on implementation. {Lecture}
    • UltraFast Design Methodology: Design Closure - Introduces the UltraFast methodology guidelines on design closure. {Lecture}
  • HDL Techniques
    • HDL Coding Techniques - Covers basic digital coding guidelines used in an FPGA design. {Lecture}
  • Vivado Tool Flow
    • Incremental Compile Flow - Utilize the incremental compile flow when making last-minute RTL changes. {Lecture}
  • Design Techniques
    • Resets - Investigates the impact of using asynchronous resets in a design. {Lecture, Lab}
    • Register Duplication - Use register duplication to reduce high fanout nets in a design. {Lecture}
    • Pipelining - Use pipelining to improve design performance. {Lecture, Lab}
    • Synchronous Design Techniques - Introduces synchronous design techniques used in an FPGA design. {Lecture}
    • Baselining - Use Xilinx-recommended baselining procedures to progressively meet timing closure. {Lecture, Lab}
    • Synchronization Circuits -Use synchronization circuits for clock domain crossings. {Lecture}
  • Design Analysis
    • Introduction to Vivado Reports - Generate and use Vivado reports to analyze failed paths. {Lecture, Demo}
  • Version Control Systems
    • Revision Control Systems in the Vivado Design Suite - Use version control systems with Vivado design flows. {Lecture}
  • Power
    • Xilinx Power Estimator Spreadsheet - Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. {Lecture, Lab}
    • Power Management Techniques - Identify techniques used for low power design. {Lecture}
  • Synthesis and Implementation
    • Vivado Synthesis and Implementation - Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board. {Lecture}
  • Vivado IP Catalog
    • Creating and Packaging Custom IP - Create your own IP and package and include it in the Vivado IP catalog. {Lecture}
    • Designing with the IP Integrator - Use the Vivado IP integrator to create the uart_led subsystem. {Lecture, Lab}
  • Pin Planning
    • Vivado Design Suite I/O Pin Planning - Use the I/O Pin Planning layout to perform pin assignments in a design. {Lecture, Lab}
  • Timing
    • Introduction to Timing Exceptions - Introduces timing exception constraints and applying them to fine tune design timing. {Lecture, Demo, Lab}
    • Timing Closure Using Physical Optimization Techniques - Use physical optimization techniques for timing closure. {Lecture, Lab}
  • Floorplanning
    • Introduction to Floorplanning - Introduction to floorplanning and how to use Pblocks while floorplanning. {Lecture}
    • Congestion -Identifies congestion and addresses congestion issues. {Lecture}
  • Configuration
    • Introduction to FPGA Configuration - Describes how FPGAs can be configured. {Lecture}
  • Debugging
    • Vivado Design Suite Debug Methodology - Understand and follow the debug core recommendations. Employ the debug methodology for debugging a design using the Vivado logic analyzer. {Lecture}

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