UltraFast Design Methodology

• Optimizing system reset design and synchronization circuits
• Employing best practice HDL coding techniques
• Applying appropriate timing closure techniques
• Reviewing an UltraFast Design Methodology case study

Who Should Attend?

Prerequisites

• Basic HDL knowledge (VHDL or Verilog)
• Digital design knowledge and experience
• Vivado Design Suite experience or completion of either: Designing FPGAs Using the Vivado Design Suite 1 course, Designing FPGAs Using the Vivado Design Suite 2 course, and Designing FPGAs Using the Vivado Design Suite 3 course; or Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users course

Skills gained

• Describe the UltraFast design methodology checklist
• Identify key areas to optimize your design to meet your design goals and performance objectives
• Define a properly constrained design
• Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
• Build resets into your system for optimum reliability and design speed
• Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
• Identify timing closure techniques using the Vivado Design Suite
• Describe how the UltraFast design methodology techniques work effectively through case studies and lab experience

Course Outline

• UltraFast Design Methodology: Introduction - Introduces the UltraFast Design Methodology and the UltraFast Design Methodology checklist. {Lecture, Demo}
• UltraFast Design Methodology: Board and Device Planning - Introduces the methodology guidelines on board and device planning.{Lecture}
• Vivado Design Suite I/O Pin Planning - Use the I/O Pin Planning layout to perform pin assignments in a design. {Lecture, Lab}
• Xilinx Power Estimator Spreadsheet - Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. {Lecture, Lab}
• Introduction to FPGA Configuration - Describes how FPGAs can be configured. {Lecture}
• UltraFast Design Methodology: Design Creation - Introduces the UltraFast methodology guidelines on design creation. {Lecture}
• HDL Coding Techniques - Covers basic digital coding guidelines used in an FPGA design. {Lecture}
• Resets - Investigates the impact of using asynchronous resets in a design. {Lecture, Lab}
• Register Duplication - Use register duplication to reduce high fanout nets in a design. {Lecture}
• Pipelining - Use pipelining to improve design performance. {Lecture, Lab}
• Synchronous Design Techniques - Introduces synchronous design techniques used in an FPGA design. {Lecture}
• Creating and Packaging Custom IP - Create your own IP and package and include it in the Vivado IP catalog. {Lecture}
• Designing with the IP Integrator - Use the Vivado IP integrator to create the uart_led subsystem. {Lecture, Lab}
• Revision Control Systems in the Vivado Design Suite - Use version control systems with Vivado design flows. {Lecture}
• UltraFast Design Methodology: Implementation - Introduces the methodology guidelines on implementation. {Lecture}
• Vivado Synthesis and Implementation - Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board. {Lecture}
• Incremental Compile Flow - Utilize the incremental compile flow when making last-minute RTL changes. {Lecture}
• UltraFast Design Methodology: Design Closure - Introduces the UltraFast methodology guidelines on design closure. {Lecture}
• Introduction to Vivado Reports - Generate and use Vivado reports to analyze failed paths. {Lecture, Demo}
• Baselining - Use Xilinx-recommended baselining procedures to progressively meet timing closure. {Lecture, Lab}
• Introduction to Timing Exceptions - Introduces timing exception constraints and applying them to fine tune design timing. {Lecture, Demo}
• Synchronization Circuits -Use synchronization circuits for clock domain crossings. {Lecture}
• Introduction to Floorplanning - Introduction to floorplanning and how to use Pblocks while floorplanning. {Lecture}
• Congestion -Identifies congestion and addresses congestion issues. {Lecture}
• Timing Closure Using Physical Optimization Techniques - Use physical optimization techniques for timing closure. {Lecture, Lab}
• Power Management Techniques - Identify techniques used for low power design. {Lecture}
• Vivado Design Suite Debug Methodology - Understand and follow the debug core recommendations. Employ the debug methodology for debugging a design using the Vivado logic analyzer. {Lecture}

Special Comments

Please download the respective PDF of your course: *

• UltraFast_Design_Methodology_fpga-vdm_2019-2_ilt_H.pdf