Home
Gros_H_HP
Gros_H_HP
Back to
Course scheduleCourse list

Introduction to Universal Verification Methodology (UVM)

Introductory UVM training course designed to help you learn the key concepts of the Universal Verification Methodology.

This 4-day course introduces engineers to developing verification environments using the Universal Verification Methodology (UVM) library. This class shows you how to create an UVM testbench structure for your DUT, which includes both stimulus generation and analysis. The class addresses how to create test cases that generate stimulus using sequences and SystemVerilog randomization constructs. The class teaches how to write analysis components such as scoreboards and coverage collectors, and how to create, integrate, and use a register model of your DUT. A good portion of class time will be spent applying principles learned in lecture to hands-on labs.

Release date

March 1, 2016

Level

UVM 1

Training duration

4 days

Price

USD 2800 or 28 Training Credits

Course Part Number

WHDL-UVM-100

Who Should Attend?

Engineers interested in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM) library

Prerequisites

  • SystemVerilog for Verification course or equivalent experience using SystemVerilog

Software Tools

  • Questa Simulator 10.4a

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Create a UVM testbench structure using the UVM library base classes and the UVM factory
  • Declare transaction items types
  • Write test cases using sequences to generate stimulus for your DUT
  • Develop scoreboards for analysis
  • Develop a register model for your DUT and use the model for initialization and accessing DUT registers

Course Outline

  • Introduction to UVM
  • UVM Reporting Facilities
  • Transaction-Level Communication
  • UVM Transactions
  • Lab - Transactions
  • Testbench Components
  • Phasing
  • Lab - Components
  • Start and End of Simulation
  • Dynamic Construction - Introduction to the UVM Class Factory
  • Lab - Test Environment
  • Connecting to the DUT
  • Stimulus Generation: Sequences
  • Analysis Elements
  • Scoreboards, Coverage Collectors, Predictors
  • Lab - Analysis
  • Hierarchy
  • Lab - Hierarchy
  • Configurability: Test Class
  • Configurability: Factory Overrides
  • Lab - Factory Overrides
  • Configurability: Configuration Objects
  • Configurability: Configuration Database
  • Lab - Configurations
  • Stimulus Generation: More Sequences Topics
  • Lab - Multiple Sequences
  • UVM Register Model
  • Register Model Integration
  • Lab - Register Integration
  • Register Model Use
  • Lab - Register Use

Please download the respective PDF of your course: *

* The course version can be found in the training registration form