This webinar is free to watch. A link to the recording will be provided shortly after registration.
As design complexity increases, it becomes necessary to test our designs at a system level. The Universal Verification Methodology (UVM) is the most state-of-the-art way to conduct system-level testing today. This webinar will highlight one key component of UVM, the Register Access Layer (RAL) and demonstrate the power of having an abstract representation of every storage element in the design. The webinar is presented by Hardent, a leading provider of verification training, and Xilinx Authorized Training Provider.
Release dateDecember 3, 2018
Skills gainedAfter completing this comprehensive training, you will have the necessary skills to:
- Discover the structure of a basic UVM testbench and how the RAL integrates within it
- Learn about the RAL and how it can help when designs and especially memory maps are changing daily
- Learn about the rich RAL APIs available to a test writer to verify individual registers or even whole groups of registers in a block
- Identify the best way to get up to speed on UVM and the RAL
* The course version can be found in the training registration form