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Xilinx & Verification Training Courses
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Webinar: An Introduction to the UVM Register Layer (REL)

This pre-recorded webinar provides an introduction to the UVM Register Layer.

As design complexity increases, it becomes necessary to test our designs at a system level. The Universal Verification Methodology (UVM) is the most state-of-the-art way to conduct system-level testing today. This webinar will highlight one key component of UVM, the Register Access Layer (RAL) and demonstrate the power of having an abstract representation of every storage element in the design. The webinar is presented by Hardent, a leading provider of verification training, and Xilinx Authorized Training Provider.

Release date

December 3, 2018

Level

Training duration

Price

Free

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Discover the structure of a basic UVM testbench and how the RAL integrates within it
  • Learn about the RAL and how it can help when designs and especially memory maps are changing daily
  • Learn about the rich RAL APIs available to a test writer to verify individual registers or even whole groups of registers in a block
  • Identify the best way to get up to speed on UVM and the RAL

* The course version can be found in the training registration form

Related Courses

Introduction to UVM

View course

Introduction to UVM (On-Demand)

View course
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Introduction to UVM
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Upcoming Sessions
Mar 15–18
Introduction to UVM
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Mar 16–18
Embedded System Design for the Zynq UltraScale+ MPSoC
Register
Mar 17–18
Xilinx Partial Reconfiguration Tools and Techniques
Register
Mar 22–23
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Complete Course Schedule
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I’ve worked with Hardent for many years and have recommended them a few times in the past. Hardent has always been extremely successful with their clients. They have many flexible ways of working with a client and will negotiate a mutually beneficial solution.

In our case, they just log into our servers and we are in constant contact via IM, email, phone, etc., but they have all their own design tools as well, so they can work either way. Being in the same time zone makes working with them easy. I am sure you will be happy with the outcome of their work. They’ll hit the ground running much faster than a single contractor would.

Marshall Johnson
Sr. Director Global ASIC/FPGA/IP Development
ADVA Optical Networking
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