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Webinar: How to Use the Versal ACAP Programmable Network on Chip (NoC) (REL)

Pre-recorded webinar offering an overview of the Versal ACAP Network on Chip (NoC).

You might be asking “what’s a NoC?” This webinar will introduce you to the Xilinx Versal programmable network on chip (NoC), a key design element in the Versal ACAP architecture.

Moore’s law requires a rethinking of how to move data through a large, heterogeneous device like the Versal ACAP.

There will also be a demonstration on how to implement the NoC in design using the Vivado IP Integrator tool.

Release date

May 25, 2021

Level

Training duration

Price

Free

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Recognize why Versal ACAP requires the NoC
  • Appreciate what the NoC provides 
  • Understand how to direct the quality of services of the NoC in design  

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Related Courses

Designing with the Versal ACAP: Network on Chip

View course

Programmable Logic Architecture for the Versal ACAP

View course

Embedded Processor Architecture for the Versal ACAP

View course
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Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

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Free Webinar

May 5 | 14:00 EST
Developing Algorithms for Versal ACAP: Optimization

Includes a live Q&A session with our trainer Reg Zatrepalek!

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