Xilinx & Functional Verification Training

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Webinar: Zynq UltraScale+ MPSoC Booting and Configuration (REL)

This webinar is free to watch. A link to the recording will be provided shortly after registration.

Zynq UltraScale+ MPSoCs support the ability to boot from different devices such as a QSPI flash, an SD card, USB Device Firmware Upgrade (DFU) host, and the NAND flash drive. This webinar will discuss the boot flow on Zynq UltraScale+ MPSoC devices and illustrate the tools required to generate the necessary boot image. The webinar is presented by Xilinx Authorized Training Provider Hardent.

Release date

January 23, 2018

Level

Training duration

Price

Free

Skills gained

After completing this comprehensive training, you will have the necessary skills to:

Discover the processing units involved in boot-up and the order of their involvement
Get an overview of the firmware components run during bootup and how they can be configured
Learn about the key components or partitions that make up a boot image
Understand the functionality of the tools and files required to generate a boot image

* The course version can be found in the training registration form

December 6, 2018

Vivado Design Analysis for Performance

Useful commands for design analysis in the Vivado Design Suite that will help you save time and meet your performance goals! More and more FPGA designs these days have requirements that demand a wide and fast data processing pipeline. This is especially true with video pipelines processing streams of 8K at 120Hz or telecommunication applications […]

November 27, 2018

Hardent & Willamette HDL Named by Breker Verification Systems As Portable Test & Stimulus Standard (PSS) Training Provider For Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Upcoming Sessions

Jan 23–25

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Jan 28–30

Embedded System Design for the Zynq UltraScale+ MPSoC

Jan 28–31

SystemVerilog for Verification

Jan 28–31

Introduction to Universal Verification Methodology (UVM)

Complete Course Schedule

Vivado Design Analysis for Performance

Useful commands for design analysis in the Vivado Design Suite that will help you save time and meet your performance goals! More and more FPGA designs these days have requirements that demand a wide and fast data processing pipeline. This is especially true with video pipelines processing streams of 8K at 120Hz or telecommunication applications […]

Hardent & Willamette HDL Named by Breker Verification Systems As Portable Test & Stimulus Standard (PSS) Training Provider For Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Hardent and Willamette HDL Develop New Portable Test and Stimulus Standard Training Course

New PSS training course equips engineers using Cadence Perspec with the skills needed to accelerate SoC verification.

Upcoming Sessions

Jan 23–25

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Jan 28–30

Embedded System Design for the Zynq UltraScale+ MPSoC

Jan 28–31

SystemVerilog for Verification

Jan 28–31

Introduction to Universal Verification Methodology (UVM)

Complete Course Schedule

Contact Hardent

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

,

QC

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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