Home
  • About Us
    • History
    • Mission
    • Team
    • Partners & Memberships
    • Customer Stories
  • Applications
    • Video
    • Automotive
    • Aerospace & Defense
    • Industrial
    • Telecommunications
  • News
    • Press Releases
    • Blog
    • Events
  • Careers
  • Contact
  • LinkedIn
  • Twitter
Xilinx & Verification Training Courses
Quality training delivered by industry experts
Back to
Course scheduleCourse list

Designing with Versal AI Engine 1

This 2-day training course is designed to give you an introduction to the Xilinx Versal AI Engine.

This course describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and AI Engines, and how to utilize the AI Engine library for faster development.

The emphasis of this course is on:
  • Illustrating the AI Engine architecture
  • Designing single AI Engine kernels
  • Designing multiple AI kernels using data flow graphs with the Vitis™ IDE
  • Describing the Vitis platform execution model and XRT
  • Reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL)
  • Analyzing and debugging kernel performance

Release date

November 2020

Level

ACAP 2

Training duration

2 days

Price

USD 1800 or 18 Training Credits

Course Part Number

ACAP AIE1

Who Should Attend?

Software and hardware developers, system architects, and anyone who needs to accelerate their software applications using Xilinx devices

Prerequisites

  • Comfort with the C/C++ programming language
  • Software development flow
  • Vitis software for application acceleration development flow

Software Tools

  • Vitis unified software platform 2020.2

Hardware

  • Architecture: Xilinx Versal ACAPs

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Describe the Versal ACAP architecture at a high level
  • Describe the various engines in the Versal ACAP device and the motivation behind the AI Engine
  • Describe the architecture of the AI Engine
  • Describe the memory access structure for the AI Engine
  • Describe the full application acceleration flow with the Vitis tool
  • Enumerate the toolchain for Versal AI Engine programming
  • Explain what intrinsic functions are
  • Program a single AI Engine kernel
  • Program multiple AI Engine kernels using static data flow (SDF) graphs

Course Outline

  • Overview of Versal ACAP Architecture - Provides an overview of the Versal architecture at a high level and describes the various engines in the Versal ACAP, such as the Scalar Engines, Adaptable Engines, and Intelligent Engines. Also describes how the AI Engine in the Versal ACAP meets many dynamic market needs. {Lecture}
  • Introduction to the Versal AI Engine Architecture - Introduces the architecture of the AI Engine and describes the AI Engine interfaces that are available, including the memory, lock, core debug, cascaded stream, and AXI-Stream interfaces. {Lecture}
  • Versal AI Engine Memory and Data Movement - Describes the memory module architecture for the AI Engine and how memory can be accessed by the AI Engines in the AI Engine arrays. {Lecture}
  • Versal AI Engine Tool Flow - Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform. {Lecture, Lab}
  • Application Partitioning on Versal ACAPs - Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal ACAP. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal ACAP. {Lecture}
  • Data Types: Scalar and Vector Data Types - Provides an AI Engine functional overview and identifies the supported vector data types and high-width registers for allowing single-instruction multiple-data (SIMD) instructions. {Lecture}
  • Intrinsic Functions - Describes what intrinsic functions are, the three types of vector management operations using intrinsic functions (load and store, element conversion, and lane insertion/extraction), multiplication functions, and application-specific functions. {Lecture}
  • Window and Streaming Data APIs - Describes window and streaming APIs and reviews the various window operations for kernels. Also discusses using overlapping data and various data movement use cases. {Lecture}
  • The Programming Model: Single Kernel - Reviews the AI Engine kernel programming flow for programming and building a single kernel. Also illustrates the steps to create, compile, simulate, and debug a single kernel program. {Lecture, Lab}
  • The Programming Model: Introduction to the Data Flow Graph - Provides the basics of the data flow graph model and graph input specifications for AI Engine programming. Also reviews graph input specifications, such as the number of platforms and ports. {Lecture}
  • The Programming Model: Multiple Kernels Using Graphs - Describes the static data flow (SDF) graph and demonstrates the steps to create a graph and set the runtime ratio and graph control APIs from the main application program. {Lecture, Lab}

Please download the respective PDF of your course: *

  • Designing_with_Versal_AI_Engine_1_acap-aie1_2020-2_ilt_H.pdf

* The course version can be found in the training registration form

Related Course

Designing with Versal AI Engine 2

View course
Contact HardentContact me
Your Trainer, Reg
Have a question about the course?

Course Schedule

  • Feb 16–17, 2021
    Live E-Learning
    Register
  • Mar 24–25, 2021
    Live E-Learning
    Register
Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
Upcoming Sessions
Jan 19–20
Embedded Design with PetaLinux Tools
Register
Jan 20–21
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Jan 21
Migrating to the Vitis Embedded Software Development IDE Workshop
Register
Jan 26
Designing with the Versal ACAP: Network on Chip
Register
Complete Course Schedule
Latest News
Contact Us
Hardent Announces Expansion of Xilinx Training in the USA
Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.
More
Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies
PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.
More
Hardent Becomes Authorized Microchip Design Partner
FPGA design services and support from Hardent will enable Microchip customers to get their products to market more quickly.
More
Upcoming Sessions
Jan 19–20
Embedded Design with PetaLinux Tools
Register
Jan 20–21
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Jan 21
Migrating to the Vitis Embedded Software Development IDE Workshop
Register
Jan 26
Designing with the Versal ACAP: Network on Chip
Register
Complete Course Schedule
Contact Hardent
Your Trainer, Reg
Have a question about the course?
HardentMontreal
450 rue Saint-Pierre, suite 300
Montreal
,
QC
H2Y 2M9
Canada
T +1 (514) 284-5252
F +1 (514) 284-5052
Tick to hear more from Hardent by email. This includes our newsletter, details about offers, new courses, and events. You can opt out at any time. For further information, please refer to our privacy policy.

We made the decision to work with Hardent as we felt confident that their strategic approach to the development process, combined with their technical expertise and training credentials, would help us to successfully reach our end goal and equip our in-house team with the electronic design knowledge to complete not just this project but other projects in the future.

Stefan Grigoras
Operations Manager
NDT Technologies Inc.
More testimonials
Training Partners
WHDL logo
Hardent © 2002-2021.
All rights reserved.
  • Privacy Policy
We use cookies to ensure that we give you the best experience on our website. By continuing to use this website, you consent to our use of cookies. OK