Designing with Versal AI Engine 1

• Illustrating the AI Engine architecture
• Designing single AI Engine kernels
• Designing multiple AI kernels using data flow graphs with the Vitis™ IDE
• Describing the Vitis platform execution model and XRT
• Reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL)
• Analyzing and debugging kernel performance

Who Should Attend?

Prerequisites

• Comfort with the C/C++ programming language
• Software development flow
• Vitis software for application acceleration development flow

Skills gained

• Describe the Versal ACAP architecture at a high level
• Describe the various engines in the Versal ACAP device and the motivation behind the AI Engine
• Describe the architecture of the AI Engine
• Describe the memory access structure for the AI Engine
• Describe the full application acceleration flow with the Vitis tool
• Enumerate the toolchain for Versal AI Engine programming
• Explain what intrinsic functions are
• Program a single AI Engine kernel
• Program multiple AI Engine kernels using static data flow (SDF) graphs

Course Outline

• Overview of Versal ACAP Architecture - Provides an overview of the Versal architecture at a high level and describes the various engines in the Versal ACAP, such as the Scalar Engines, Adaptable Engines, and Intelligent Engines. Also describes how the AI Engine in the Versal ACAP meets many dynamic market needs. {Lecture}
• Introduction to the Versal AI Engine Architecture - Introduces the architecture of the AI Engine and describes the AI Engine interfaces that are available, including the memory, lock, core debug, cascaded stream, and AXI-Stream interfaces. {Lecture}
• Versal AI Engine Memory and Data Movement - Describes the memory module architecture for the AI Engine and how memory can be accessed by the AI Engines in the AI Engine arrays. {Lecture}
• Versal AI Engine Tool Flow - Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform. {Lecture, Lab}
• Application Partitioning on Versal ACAPs - Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal ACAP. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal ACAP. {Lecture}
• Data Types: Scalar and Vector Data Types - Provides an AI Engine functional overview and identifies the supported vector data types and high-width registers for allowing single-instruction multiple-data (SIMD) instructions. {Lecture}
• Intrinsic Functions - Describes what intrinsic functions are, the three types of vector management operations using intrinsic functions (load and store, element conversion, and lane insertion/extraction), multiplication functions, and application-specific functions. {Lecture}
• Window and Streaming Data APIs - Describes window and streaming APIs and reviews the various window operations for kernels. Also discusses using overlapping data and various data movement use cases. {Lecture}
• The Programming Model: Single Kernel - Reviews the AI Engine kernel programming flow for programming and building a single kernel. Also illustrates the steps to create, compile, simulate, and debug a single kernel program. {Lecture, Lab}
• The Programming Model: Introduction to the Data Flow Graph - Provides the basics of the data flow graph model and graph input specifications for AI Engine programming. Also reviews graph input specifications, such as the number of platforms and ports. {Lecture}
• The Programming Model: Multiple Kernels Using Graphs - Describes the static data flow (SDF) graph and demonstrates the steps to create a graph and set the runtime ratio and graph control APIs from the main application program. {Lecture, Lab}

Please download the respective PDF of your course: *

• Designing_with_Versal_AI_Engine_1_acap-aie1_2020-2_ilt_H.pdf