Custom processor accelerators are quickly becoming standard practice for reaching system performance goals. This one-day introduction to the accelerator development flow focuses on how to measure system performance, determine what software functionality should be moved to hardware, how to assemble a custom accelerator using the Vivado HLS tool, add the custom accelerator to a Zynq All Programmable SoC design, and finally measure accelerated performance. Emphasis is placed on the Zynq AP SoC's architectural features that make coupling an accelerator to the multi-processor core a possibility as well as the many techniques for implementing accelerated systems. Discussion of typical tradeoffs that a system architect will likely make is also included. The specifics of the accelerator itself is secondary as the focus is on how to integrate an accelerator rather than accelerator design techniques.
Release dateJune 2015
Training duration1 day
PriceUSD 800 or 8 Training Credits
Course Part NumberEMBD-ZACCEL
Who Should Attend?System architects who are interested in architecting a system on a chip using the Zynq All Programmable SoC with hardware acceleration.
- Digital system architecture design experience
- Basic understanding of microprocessor architecture
- Basic understanding of C programming
- Basic understanding of system architecture
- Architecture: Zynq-7000 All Programmable SoC
- Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard
Skills gainedAfter completing this comprehensive training, you will have the necessary skills to:
- Identify which system architecture best fits the design needs: data flow or accelerator
- Determine if software is meeting behavioral and performance specifications
- Profile an existing application to determine which functions are candidates for moving to hardware; design, from the ground up, an appropriately architected accelerator system
- Construct an accelerator using the Vivado HLS tool
- Assemble an embedded system using the Vivado IP integrator, including the custom accelerator
- Architect a memory system and memory access to best support an accelerator architecture
- Measure the performance of the complete system, including AXI loading
- Introduction and Agenda
- Zynq AP SoC Architecture Support for Accelerators
- Lab 1: Impact of Port Selection on System Performance
- Accelerator Development Process
- Lab 2: Measuring Performance and Profiling
- Coding Techniques for Accelerators
- Developing the Accelerator Using HLS
- Lab 3: Building a Hardware Accelerator Using the Vivado HLS Tool
- Building the Embedded Design Using IPI
- Lab 4: Building an Accelerated Embedded System (Accelerator Model)
- Memory Concepts
- Measuring Embedded System Performance
- Lab 5: Measuring Accelerated System Performance
- Lab 1: Impact of Port Selection on System Performance - The Zynq AP SoC has a number of ports. Connecting the accelerator to the wrong one could significantly hamper system performance. This lab explores the balance between loading the AXI ports and processor performance.
- Lab 2: Measuring Performance and Profiling - Here you will learn how to measure system performance and determine through profiling which software functions should be moved to hardware in the form of an accelerator.
- Lab 3: Building a Hardware Accelerator Using the Vivado HLS Tool - The Vivado HLS tool is a powerful C/C++ to netlist building tool that greatly facilitates converting software functions to hardware accelerators.
- Lab 4: Building an Accelerated Embedded System (Accelerator Model) - This lab explores how the accelerator can be attached to the PS.
- Lab 5: Measuring Accelerated System Performance - Having completed a full build of the accelerated embedded system, you will now confirm proper behavior and overall system performance.
Please download the respective PDF of your course: *
* The course version can be found in the training registration form