Zynq training course covering the main features and benefits of the Zynq device architecture.
The Xilinx Zynq System on a Chip (SoC) provides
a new level of system design capabilities. This course, available in-person or online, provides system architects
with the knowledge to effectively architect a Zynq SoC.
This course presents the features and benefits of the Zynq architecture for making decisions on how to best architect a Zynq SoC project. It covers the architecture of the ARM Cortex-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq SoC.
The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.
This course presents the features and benefits of the Zynq architecture for making decisions on how to best architect a Zynq SoC project. It covers the architecture of the ARM Cortex-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq SoC.
The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.
Release date
August 2016Level
Embedded Hardware 3Training duration
2 daysPrice
USD 1600 or 16 Training CreditsCourse Part Number
EMBD-ZSAWho Should Attend?
System architects who are interested in architecting a system on a chip using the Zynq SoC.Prerequisites
- Digital system architecture design experience
- Basic understanding of microprocessor architecture
- Basic understanding of C programming
- Basic HDL modeling experience
Software Tools
- Vivado Design or System Edition 2018.1
Hardware
- Architecture: Zynq-7000 SoC
- Demo board: Zynq-7000 SoC ZC702 or ZedBoard*
Skills gained
After completing this comprehensive training, you will have the necessary skills to:- Describe the architecture and components that comprise the Zynq SoC processing system (PS)
- Relate a user design goal to the function, benefit, and use of the Zynq SoC
- Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals
- Analyze the tradeoffs and advantages of performing a function in software versus PL
Course Outline
- Overview {Demo}
- Application Processor Unit (APU) {Lab}
- Neon Co-Processor
- Input/Output Peripherals {Demo}
- Low-Speed Peripherals: Overview {Lab}
- Low-Speed Peripherals: UART {Demo}
- Low-Speed Peripherals: CAN {Demo}
- Low-Speed Peripherals: I2C
- Low-Speed Peripherals: SD/SDIO
- Low-Speed Peripherals: GPIO
- High-Speed Peripherals: USB
- High-Speed Peripherals: Gigabit Ethernet {Lab}
- DMA Controller (DMAC) {Lab}
- DMA: Introduction and Features
- DMA: Block Design and Interrupts
- DMA: Read and Write
- AXI: Introduction
- AXI: Variations
- AXI: Transactions {Demo, Lab}
- PS-PL Interface {Demo, Lab}
- Booting {Lab}
- Memory Resources {Demo}
- Meeting Performance Goals {Lab}
- Hardware Design {Lecture}
- Software Design {Demo, Lab}
- Debugging {Lab}
- Tools and Reference Designs
Topic Descriptions
- Overview – Provides a general overview of the Zynq SoC.
- Application Processor Unit (APU) – Explores the individual components that comprise the APU.
- Neon Co-Processor – Describes the Neon co-processor that is the companion to each Cortex-A9 processor.
- Input/Output Peripherals – Introduces the components that comprise the IOP block of the Zynq device PS.
- Low-Speed Peripherals: Overview – Introduces the low-speed peripherals in the Zynq SoC.
- Low-Speed Peripherals: UART – Introduces the UART low-speed peripheral.
- Low-Speed Peripherals: CAN – Introduces the CAN low-speed peripheral.
- Low-Speed Peripherals: I2C – Introduces the I2C low-speed peripheral.
- Low-Speed Peripherals: SD/SDIO – Introduces the SD/SDIO low-speed peripheral.
- Low-Speed Peripherals: GPIO – Introduces the GPIO low-speed peripheral.
- High-Speed Peripherals: USB – Introduces the USB high-speed peripheral.
- High-Speed Peripherals: Gigabit Ethernet – Introduces the Gigabit Ethernet high-speed peripheral.
- DMA Controller (DMAC) – Explores the operation of the DMAC, which is located in the APU.
- DMA: Introduction and Features – Introduces the direct memory access controller.
- DMA: Block Design and Interrupts – Introduces the DMA block design and the DMA interrupts.
- DMA: Read and Write – Introduces the concepts behind DMA reading and writing.
- AXI: Introduction – Introduces the AXI protocol.
- AXI: Variations – Describes the differences and similarities among the three primary AXI variations.
- AXI: Transactions – Describes different types of AXI transactions.
- PS-PL Interface – Describes in detail the PS interconnect and how it affects PL architecture decisions.
- Booting – Explains the boot process of the PC and configuration of the PL.
- Memory Resources – Explains the operation of the on-chip (OCM) memory and various memory controllers located in the PS.
- Meeting Performance Goals – Focuses on Zynq device performance, including DDR access from the PL, DMA considerations, and power control and reduction techniques.
- Hardware Design – Discusses the use and configuration of the PS in a hardware design.
- Software Design – Explores the software side of the Zynq device.
- Debugging – Introduces debug tools and methodology on the Zynq SoC.
- Tools and Reference Designs – Describes Xilinx-provided reference design platforms, use cases, and third-party operating systems and tools for the Zynq SoC.
Special Comments
*The listed course price is for the in-person training. The cost of the online training is $2000 or 20 Training Credits and includes a ZedBoard that is yours to keep after the training is completed. If you already own a ZedBoard, the overall cost of the online training remains at $1600 or 16 Training Credits.Please download the respective PDF of your course: *
* The course version can be found in the training registration form