Useful commands for FPGA design analysis in the Vivado Design Suite that will help you save time and meet your performance goals!
More and more FPGA designs these days have requirements that demand a wide and fast data processing pipeline. This is especially true with video pipelines processing streams of 8K at 120Hz or telecommunication applications where bandwidths over 300 GHz are required.
In order to achieve the required performance, and have a design that will place and route (PAR) without timing errors, it is now more important than ever before to do early FPGA design analysis. By doing this, you can achieve the required performance in less time, while having a design that will place and route (PAR) without timing errors.
FPGA Design Analysis: When Is The Best Time To Do It?
The timing closure process is usually done after the RTL has been completed and mostly tested. Usually, the only paths that are modified are the ones that fail timing. By doing some early analysis during the RTL writing and verification phase, it is possible to reduce the time required to close timing and catch structural problems in the FPGA early, thus saving redesign time.
This article summarizes useful commands that you can use to analyze your FPGA design. These commands should be used after the first draft of the RTL module while the code sanity is performed.
Max Logic Level Depth
Running at a high frequency limits the amount of combinatorial logic between 2 registers. The maximum logic level for your design will depend on the target device and the type of combinatorial logic used. The following command will give you a break down of the logic level in your design:
report_design_analysis -logic_level_distribution -name myanalysis
We can see that in this design there are 14 paths with a depth of 10.
To get a detailed analysis for one logic level, you can use the following command:
report_design_analysis -end_point_clock clk -logic_levels 10 -timing -return_timing_paths
It will return a list of all the paths that have an endpoint in clk and have a logic level of 10 only. See the Useful Commands section below for a way to display these paths.
Pipelining the dataflow or balancing the logic around the register are usually good ways to reduce the number of logic levels.
Max Fanout
Another limiting factor is when a net is driving a lot of resources. This will generate a longer path delay and can cause congestion problems.
The following command will give you a list of elements driving more than 50 resources:
report_high_fanout_nets -fanout_greater_than 50 -max_nets 100 
If the driving net is a register, the tool is able to replicate it. But if it is combinatorial logic, it will not be able to perform the replication. For these combinatorial logic drivers, it is a good idea to pipeline them and let the tool replicate the register automatically.
RAMs Pipeline
To achieve maximum performance, the Block RAM needs to be pipelined at the input and at the output. This can be easily verified using the following commands:
report_timing -to [all_rams] -max_paths 5000 -setup -name mytime
report_timing -from [all_rams] -max_paths 5000 -setup -name mytime
In this example, we can see that the level is 4. The code should be modified so it is 1.
DSP Pipeline
Like the Block RAM, the DSPs need to have pipelined registers to operate at their maximum frequency.
You can use the following commands to verify this.
report_timing -to [all_dsps] -max_paths 5000 -setup -name mytime
report_timing -from [all_dsps] -max_paths 5000 -setup -name mytime
Useful Commands
Once you have identified a path that is causing issues, you can use the following command to show it in the schematic view and get a better understanding of what is going on.
select_objects [get_nets <path of the net>]
In order to easily test a module, Vivado can be used in Out Of Context (OOC) mode.
This mode will let you synth, place, and route the module without having to worry about pins.
This option needs to be set in the Synthesis settings:
-mode out_of_context 
Summary: Early FPGA Design Analysis Saves Valuable Time
The commands shown above are only a small part of the tools available for FPGA design analysis, but they can help you to close timing and reduce the bitstream generation length.
As additional reading, I would recommend that you also familiarize yourself with commands to analyse the clock domain crossers and the design complexity (see UG 906).
Further Reading: Xilinx Vivado Design Suite
- UG 949: UltraFast Design Methodology User Guide for the Vivado Design Suite
- UG 906: Design Analysis and Closure
- UG 903: Using Constraints
- UG 835: Tcl Command Reference Guide
- Vivado Timing Closure – Suggestions for resolving timing issues seen in Vivado
Author Bio
Julien Gagnon is a hardware designer at Hardent with 12 years of experience. He works across many different aspects of FPGA development projects including verification, board design, Verilog design, architecture, and flows. He is frequently called on to support customers across a number of industries with designs and flows using Xilinx FPGAs and tools.
Having trouble meeting timing? Need help with your FPGA design analysis?
