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    Mathematically Lossless Video Compression IP Cores
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Mathematically Lossless Video Compression IP Cores

Hardent’s mathematically lossless video compression IP cores use a cutting-edge compression algorithm to deliver impressive compression ratios, while preserving a bit-exact representation of the original data captured.

Hardent lossless video compression (HLVC) has been specifically designed to facilitate the challenges associated with capturing, processing, storing, and playing back large amounts of raw data captured by image sensors, LIDAR, and cameras as part of Advanced Driver-Assistance Systems (ADAS).

Why use mathematically lossless video compression?

With HLVC, you can reduce overall storage space and memory footprint, lower transfer bandwidth on transmission links, as well as reduce the overall power consumption of your design, all while preserving a bit-exact representation of the original data.

Key features of HLVC include:

  • True mathematically lossless (bit-exact) compression
  • Support for a wide variety of raw data
  • Small footprint for FPGA & ASIC design
  • Ultra low-latency performance
  • Real-time encoding/decoding capabilities for both FPGA and ASIC design
  • Optional software codec available for real-time and faster than real-time performance

Hardent Lossless Video Compression (HLVC) IP Cores

Find out more about our HLVC IP cores in the product briefs below.

DOWNLOAD HLVC PRODUCT BRIEFS
  • HLVC Encoder IP Core
  • HLVC Decoder IP Core
Mathematically Lossless Video Compression IP Cores
HLVC is designed to facilitate the management of large volumes of raw data captured by automotive image sensors.
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Frame Buffer Compression IP Subsystem for TCON IC Manufacturers Launched by Hardent
Proven IP subsystem enables TCON IC manufacturers to leverage new Embedded DisplayPort low power features and significantly reduce frame buffer area using VESA DSC.
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