Training is a valuable tool for engineering teams wanting to increase productivity, but sometimes there is simply not enough time or money available to travel to a classroom location.
Hardent’s new on-demand SystemVerilog for Verification training course bridges this gap and provides students all-around flexibility in learning to use SystemVerilog technology in their verification process.
We are pleased to announce a brand-new on-demand SystemVerilog for Verification training course designed to give you the freedom to learn SystemVerilog at a pace that fits your schedule.
The training has been designed and developed by verification experts who have extensive practical verification and teaching experience.
What does Hardent’s on-demand SystemVerilog for Verification training cover?
The course is divided into three sections covering foundational principles, object-oriented programming, and randomization & functional coverage. Each section consists of self-paced video lessons and practical lab exercises for every major topic covered.
You will learn how to:
- Use SystemVerilog data types, array types, and structures in your testbenches
- Develop Object Oriented testbenches
- Apply SystemVerilog constrained randomization to stimulus generation
- Apply functional coverage to analyze your testbench
- Adopt a coding style that makes it easier to later migrate to the Universal Verification Methodology (UVM)
What’s included in the training package?
- 30 days access to training videos and hands-on lab exercises
- Printed lab book delivered to your door
- Certificate of completion
- Access to 3 follow-on online group Q&A sessions with a verification expert
Watch this short video to get an overview of Hardent’s on-demand SystemVerilog for Verification training.
Why take a SystemVerilog for verification training course?
As designs become more complex, so does the verification process. As much as 60% of your development time will be spent on verification. SystemVerilog is a combined hardware description language and hardware verification language widely considered to be the language of choice for verification engineers. Developed in 2005 as a superset of Verilog, it incorporates numerous improvements to the original Verilog HDL.
These changes can make getting up to speed with SystemVerilog a challenging and time-consuming task. By taking an on-demand SystemVerilog for verification training, you will have the chance to learn key concepts at your own pace and jump start the integration of SystemVerilog into your verification process.
Meet Your Trainer: Tim Corcoran
Tim has been developing and teaching verification for nearly three decades. He has extensive experience with SystemVerilog and UVM and has taught thousands of students around the world.