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    DisplayPort 1.4 IP Subsystem
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DisplayPort 1.4 IP Subsystem

Take advantage of the full DisplayPort 1.4 feature set, including VESA DSC and FEC, to support resolutions up to 8K.

Hardent’s DisplayPort 1.4 IP includes support for VESA DSC 1.2a, a visually lossless video compression technology that increases the DisplayPort data transfer capacity by 3X, while using the same physical link speed.

With DSC’s bandwidth reduction, the DisplayPort 1.4 standard can be used to transport Ultra High Definition (UHD) and High Dynamic Range (HDR) video streams across a single DisplayPort interface for pro A/V applications such as digital signage, high-end projectors, and test equipment.

Hardent’s DisplayPort 1.4 IP subsystem targets customers using Xilinx® UltraScale™ and UltraScale+™ devices and delivers an out-of-the-box IP solution to help designers achieve a faster time-to-market.

Key Features

  • Complete DisplayPort 1.4 IP subsystem solution with support for VESA Display Stream Compression (DSC) and Forward Error Correction (FEC)
  • Fully compliant with the DisplayPort 1.4a Standard
  • Supports up to 4 lanes at HBR3 rate (8.1 Gbits/sec)
  • Configurable maximum display resolution up to 8K (FUHD) 60fps in RGB 444
  • All color spaces supported by DSC v1.2a and component bit depth up to 12 bits

DisplayPort 1.4 IP Subsystem for Xilinx FPGAs

The complete DisplayPort 1.4 IP subsystem includes:

  • Xilinx Video PHY Controller & DisplayPort 1.4 TX or RX Subsystem IP
  • Hardent VESA DisplayPort 1.4 Forward Error Corrector (FEC) TX or RX IP for Xilinx FPGAs
  • Hardent VESA Display Stream Compression (DSC) 1.2a Encoder or Decoder IP for Xilinx FPGAs
  • Reference design with Vivado Design Suite & SDK project files
  • Documentation for each IP
  • Comprehensive integration guide
  • Software drivers and user application example
  • Technical support from the Hardent engineering team
Download Product Information
  • DisplayPort 1.4 TX IP Subsystem for Xilinx FPGAs
  • DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
DisplayPort 1.4 IP subsystem for Xilinx FPGAs enabling resolutions up to 8K
DisplayPort 1.4 IP subsystem for Xilinx FPGAs enabling resolutions up to 8K
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Alain Legault
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Time to market was one of our first considerations in choosing Hardent to design a PCI communication bridge. They grasped the project requirements in a matter of days. Their impressive expertise and responsiveness made the development process very smooth, as if they were working right down the hall.

Nicolas Gonthier
Hardware Design Manager
Verint Systems Canada Inc.
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