Blog
December 6, 2018
FPGA Design Analysis Using the Vivado Design Suite
Useful commands for FPGA design analysis in the Vivado Design Suite that will help you save time and meet your performance goals!
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MoreMarch 14, 2018
New SystemVerilog Online Training Course
Hardent’s new SystemVerilog for Verification online training course gives you the flexibility to learn SystemVerilog at your own pace. You'll learn through practical lab exercises based on real scenarios, and even get a certificate!
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MoreDecember 1, 2017
CES 2018: The Latest In VESA DSC Video Compression Technology
For the fourth year running we will be kicking off the New Year in Las Vegas at the biggest tech event of the year: CES! Join us at the DisplayPort booth where we will be showcasing the very latest in video compression technology.
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MoreCompressed video images can be affected by transmission errors. Using the example of DisplayPort 1.4 and VESA Display Stream Compression (DSC), we’re taking a look at how Reed-Solomon Forward Error Correction (FEC) code is used to improve the resiliency to link errors when transporting compressed video.
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More2017
August 28, 2017
New 3-day Zynq UltraScale+ MPSoC Training Course
2016
2015
April 9, 2015