Blog

Useful commands for design analysis in the Vivado Design Suite that will help you save time and meet your performance goals! More and more FPGA designs these days have requirements that demand a wide and fast data processing pipeline. This is especially true with video pipelines processing streams of 8K at 120Hz or telecommunication applications where bandwidths over 300 GHz are required. …

Training is a valuable tool for engineering teams wanting to increase productivity, but sometimes there is simply not enough time or money available to travel to a classroom location. Hardent’s new on-demand SystemVerilog for Verification training course bridges this gap and provides students all-around flexibility in learning to use SystemVerilog technology in their verification process. …

For the fourth year running we will be kicking off the New Year in Las Vegas at the biggest tech event of the year: CES! Join us at the DisplayPort booth where we will be showcasing the very latest in video compression technology. …

Compressed video images can be affected by transmission errors. Using the example of DisplayPort 1.4 and VESA Display Stream Compression (DSC), we’re taking a look at how Reed-Solomon Forward Error Correction (FEC) code is used to improve the resiliency to link errors when transporting compressed video. …