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ECC/Reed-Solomon FEC IP Cores

Hardent’s ECC/Reed-Solomon FEC IP portfolio targets a wide range of applications on both FPGA and ASIC technology. In addition to IP cores targeted at specific applications, we also offer customized Reed-Solomon or BCH encoder and decoder IP cores based on customer-specific parameters. As your IP provider, we will leverage our extensive system-level design expertise to deliver a complete IP solution targeted to meet the unique requirements of your application.

Error-Correcting Code (ECC) and Forward Error Correction (FEC) are used in information systems to detect and correct errors that may be introduced in a noisy or unreliable data channel environment. Although both ECC and FEC mean the same thing, the term FEC is normally used in data transmission systems, while ECC is used for storage and other types of systems.

ECC/FEC is made possible by adding redundant information to the data at the encoder side (or the transmitter side). The decoder (also referred to as the receiver side) then uses the redundant information to detect and correct the errors that may have been introduced in the data.

Find out more about Hardent’s ECC/Reed-Solomon FEC IP products below.

Reed-Solomon FEC IP Cores For Display Interface Applications

DISPLAYPORT 1.4 FEC IP CORES

DisplayPort 1.4 includes support for VESA Display Stream Compression (DSC) 1.2a, a visually lossless video compression algorithm. As compressed video images can be affected by transmission errors, and even a single bit error can have a catastrophic impact on the visual experience, DisplayPort 1.4 specifies Forward Error Correction (FEC) in order to improve the resiliency of the link and achieve a glitch-free visual experience. DisplayPort 1.4 uses different fixed link speeds, up to 8.1Gbps (called HBR3). Using DSC with HBR3 transmission rates, DisplayPort 1.4 can support 8K UHD (7680×4320) at 60 Hz with 10-bit color and HDR. Hardent’s DisplayPort FEC IP cores use Reed-Solomon RS(254,250) Forward Error Correction code operating on the 10 bit symbols obtained after 8b/10b encoding.

See IP Cores

Target applications include UHD monitors / automotive displays / set-top boxes, DisplayPort 1.4 / USB Type-C products, GPUs, and mobiles / tablets.

  • DisplayPort 1.4 FEC RX IP Core
  • DisplayPort 1.4 FEC TX IP Core
  • *NEW* ASIL-B Ready ISO 26262 Certified DisplayPort 1.4 FEC TX IP Core

Wondering what error correction looks like live?

Watch our DP 1.4 and FEC demo from CES 2018!

NEW HDMI 2.1 FEC IP CORES

The new HDMI 2.1 specification offers a number of significant new features and bandwidth capabilities to support higher resolution displays and faster refresh rates, including support for VESA Display Stream Compression (DSC) 1.2a. To achieve higher throughputs, HDMI 2.1 uses a new packet-based link layer. This layer converts the clock and three data lanes of original HDMI TMDS mode to three or four self-clocked links that can be operated at up to 12 Gbit/s. A versatile packet mode maps video, either uncompressed or compressed with DSC, audio, and data over the link. A Forward Error Correction (FEC) algorithm is used to correct possible transmission errors to ensure an error free transmission of the packets over the HDMI links. Hardent’s HDMI FEC IP cores implement Reed-Solomon RS(255,251) FEC code and symbol de-interleaving/de-mapping as specified by the HDMI 2.1 standard.

See IP Cores

Target applications include UHD monitors / TVs / home theaters / set-top boxes, HDMI 2.1 hubs and accessories, professional video equipment, and GPUs.

  • HDMI 2.1 FEC RX IP Core
  • HDMI 2.1 FEC TX IP Core

Custom Reed-Solomon FEC IP Cores

Hardent’s fully-configurable parallel Reed-Solomon Forward Error Correction and BCH custom IP cores can be used across a wide range of applications to produce a high-performance hardware ECC/FEC encoder/decoder circuit for any type of ASIC or FPGA technology. As our customer, you will benefit from our team’s extensive system level design expertise to ensure that this IP solution meets the requirements of your system and target application. Hardent uses a proprietary tool suite to implement the ECC/FEC function using user-defined parameters, such as the number of bits per symbol, message length, codeword length, and the number of parity symbols. The level of parallelization (symbol per clock) of the generated circuit can be specified in order to allow for optimization of clock speed and/or gate count based on the unique requirements of your application.

See IP Cores

Target applications include optical links, high-speed electrical links in automotive and consumer applications, wireless transmission, fault-tolerant SSD storage, and deep space transmission and telemetry.

  • Parallel Reed-Solomon ECC/FEC RX Custom IP Core
  • Parallel Reed-Solomon ECC/FEC TX Custom IP Core
  • Binary BCH ECC/FEC RX Custom IP Core
  • Binary BCH ECC/FEC TX Custom IP Core

Reed-Solomon FEC IP Cores For Optical Networking & Wide Area Networks

Reed-Solomon FEC codes are extensively used in optical networking to improve the Bit Error Rate (BER) of optical links to meet the high performance required by telecommunication operators. Telecom FEC codes are made to meet industry standards, governed by the ITU (International Transmission Union). Hardent offers several FEC solutions for telecommunication networks.

See IP Cores

Target applications include Optical Transmission Network (OTN), Submarine cable, HTTP, GPON as specified by the ITU-T G.709, G.975, G.984.

  • G.709 GFEC RX IP Core
  • G.709 GFEC TX IP Core
  • G.975 FEC RX IP Core
  • G.975 FEC TX IP Core

Related articles

Hardent IP Portfolio Supports New Features of HDMI 2.1 Specification

VESA DSC and Reed-Solomon FEC IP cores enable HDMI controller manufacturers and IP providers to quickly implement new features of HDMI 2.1 and support higher resolution displays. …
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Using Reed-Solomon Forward Error Correction (FEC) Code For Display Interfaces

Compressed video images can be affected by transmission errors. Using the example of DisplayPort 1.4 and VESA Display Stream Compression (DSC), we’re taking a look at how Reed-Solomon Forward Error Correction (FEC) code is used to improve the resiliency to link errors when transporting compressed video. …
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A Quick Guide to VESA Display Stream Compression

VESA Display Stream Compression (DSC) is a new standard that enables visually lossless compression for ultra-high definition display applications. This quick guide takes a look at the background to VESA DSC and how this new…
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Reed-Solomon FEC IP Cores
Hardent’s Reed-Solomon FEC IP portfolio offers customers ready-made solutions to accelerate product development.
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